AnalogAgent: Self-Improving Analog Circuit Design Automation with LLM Agents
Nanyang Technological University（南洋理工大学）；Institute for Infocomm Research（信息通信研究所）；Institute of Microelectronics（微电子研究所）；Eindhoven University of Technology（埃因霍温理工大学）；Singapore University of Technology（新加坡科技学院）
Recent advances in large language models (LLMs) suggest strong potential for automating analog circuit design. Yet most LLM-based approaches rely on a single-model loop of generation, diagnosis, and correction, which favors succinct summaries over domain-specific insight and suffers from context attrition that erases critical technical details. To address these limitations, we propose AnalogAgent, a training-free agentic framework that integrates an LLM-based multi-agent system (MAS) with self-evolving memory (SEM) for analog circuit design automation. AnalogAgent coordinates a Code Generator, Design Optimizer, and Knowledge Curator to distill execution feedback into an adaptive playbook in SEM and retrieve targeted guidance for subsequent generation, enabling cross-task transfer without additional expert feedback, databases, or libraries. Across established benchmarks, AnalogAgent achieves 92% Pass@1 with Gemini and 97.4% Pass@1 with GPT-5. Moreover, with compact models (e.g., Qwen-8B), it yields a +48.8% average Pass@1 gain across tasks and reaches 72.1% Pass@1 overall, indicating that AnalogAgent substantially strengthens open-weight models for high-quality analog circuit design automation.
PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
School of Integrated Circuits, Peking University（集成电路学院，北京大学）；Beijing Advanced Innovation Center for Integrated Circuits（北京集成电路先进创新中心）；Institute of Electronic Design Automation, Peking University（电子设计自动化研究所，北京大学）
AutoSizer: Automatic Sizing of Analog and Mixed-Signal Circuits via Large Language Model (LLM) Agents
Artificial Intelligence Department, Brookhaven National Laboratory, Upton, NY（布鲁赫斯国家实验室人工智能部）；Instrumentation Department, Brookhaven National Laboratory, Upton, NY 11973（布鲁赫斯国家实验室仪器部）
A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction
School of Electronic Science（电子科学学院）；Nanjing University（南京大学）；National Center of Technology Innovation for EDA（EDA技术创新中心）；Nanjing Tech University（南京理工大学）；School of Integrated Circuits（集成电路学院）；Southeast University（东南大学）
MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs
Department of Computer Science and Engineering, The Chinese University of Hong Kong（中国香港中文大学计算机科学与工程系）；School of Electronic Science and Engineering, Nanjing University（南京大学电子科学与工程学院）；School of Integrated Circuits, Peking University（北京大学集成电路学院）；School of Intergrated Circuits, Southeast University（东南大学集成电路学院）；School of Computer Science and Engineering, Southeast University（东南大学计算机科学与工程学院）；Department of Computer Science and Technology, University of Chinese Academy of Sciences（中国科学院大学计算机科学与技术系）；National Center of Technology Innovation for EDA（EDA技术创新国家中心）
AMSnet-q: Unsupervised Circuit Identification and Performance Labeling for AMS Circuits
Southern University of Science and Technology（南方科技大学）；University of California Los Angeles（加州大学洛杉矶分校）；Tsinghua University（清华大学）；Eastern Institute of Technology Ningbo（宁波东部技术研究院）
LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation
IBM T. J. Watson Research Center（IBM T.J.沃森研究中心）；Duke University（杜克大学）；MIT-IBM Watson AI Lab（麻省理工-IBM沃森人工智能实验室）；University of California, Los Angeles（加州大学洛杉矶分校）
LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits
IBM T. J. Watson Research Center（IBM T. J. 沃森研究中心）；Duke University（杜克大学）；MIT-IBM Watson AI Lab（麻省理工学院-IBM 沃森人工智能实验室）；New Jersey Institute of Technology（新泽西理工学院）；University of Notre Dame（圣母大学）
AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAG
Eastern Institute of Technology（东方理工大学）；University of California, Los Angeles（加利福尼亚大学洛杉矶分校）；BTD Inc.（BTD公司）；Tsinghua University（清华大学）；Institute of Digital Twin, Eastern Institute of Technology（东方理工大学数字孪生研究院）
