发表机构
Qualcomm Technologies, Inc.; UC Berkeley（高通技术有限公司; 加州大学伯克利分校）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
该研究提出RFChipAgent，一种LLM驱动的多智能体流程，用于端到端模拟/射频芯片设计自动化，经GF22FDSOI 60 GHz LNA验证，可大幅减少设计工作量并保持签核级质量，为相关EDA奠定基础。
AI 中文摘要
模拟/射频电路是数字计算与物理世界之间的关键接口，从Wi-Fi 7到6G的新兴标准对其提出了严格要求，但模拟/射频设计仍是芯片开发中劳动强度最大的步骤之一。我们提出RFChipAgent，这是一种首创的用于端到端模拟/射频电路设计自动化的大型语言模型（LLM）智能体多智能体流程，其中AI智能体在人类监督下协同编排完整设计流程。RFChipAgent围绕四大技术支柱构建：第一，带有私有逐文档FAISS索引的多模态检索增强生成（RAG）子系统，从现有工程文档中提取设计知识；第二，拓扑智能体驱动拓扑选择，原理图与测试平台智能体实现电路和测试平台的自动化组装；第三，闭环混合电路尺寸引擎结合树状Parzen估计器（TPE）与CMA-ES优化，在闭环仿真框架中评估每个候选方案；第四，带信任评分的仿真数据库积累已验证的性能数据，构建自适应优化模型以指导后续试验。我们在GF22FDSOI 60 GHz宽带毫米波低噪声放大器（LNA）拓扑系列上验证了RFChipAgent，展示了自动化拓扑生成、规格驱动的设计空间探索以及仿真器引导的优化。实验结果显示，在保持签核级验证质量的同时，设计工作量大幅减少。本研究为LLM驱动的模拟/射频电路多智能体电子设计自动化（EDA）奠定了基础。
英文摘要
Analog/RF circuits remain the critical interface between digital computation and the physical world, and emerging standards from Wi-Fi 7 to 6G place stringent demands on them, yet analog/RF design remains one of the most labor-intensive steps in chip development. We present RFChipAgent, a first-of-its-kind multi-agent flow of large language model (LLM) agents for end-to-end analog/RF circuit design automation, in which AI agents collaboratively orchestrate the complete design flow under human supervision. RFChipAgent is built around four technical pillars. First, a multimodal retrieval-augmented generation (RAG) subsystem with private per-document FAISS indexing extracts design knowledge from existing engineering documentation. Second, a topology agent drives topology selection, and a schematic and testbench agent automates circuit and testbench assembly. Third, a closed-loop hybrid circuit-sizing engine combines Tree-structured Parzen Estimator (TPE) and CMA-ES optimization, evaluating every candidate in a simulator-in-the-loop framework. Fourth, a trust-scored simulation database accumulates verified performance data and builds an adaptive optimization model that informs subsequent trials. We validate RFChipAgent on a family of GF22FDSOI 60 GHz wideband mm-wave low-noise amplifier (LNA) topologies, demonstrating automated topology generation, specification-driven design-space exploration, and simulator-guided optimization. Experimental results show substantial reductions in design effort while maintaining signoff-quality verification. This work establishes a foundation for LLM-driven multi-agent electronic design automation (EDA) for analog/RF circuits.
Comments6 pages, 4 figures. Submitted to ACM/IEEE for possible publication
