错误代码，正确结构：从不完美的LLM生成RTL学习网表表示
Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL
AI总结：
本文提出利用不完美的LLM生成RTL进行网表表示学习，通过数据增强和端到端流程，提升电路分析任务的性能。
摘要：
学习有效的网表表示本质上受到标注数据稀缺的限制，因为真实设计受知识产权（IP）保护且标注成本高昂。现有研究因此聚焦于小规模电路和干净标签，限制了对现实设计的扩展性。同时，大语言模型（LLMs）可以大规模生成寄存器传输级（RTL）代码，但其功能错误性阻碍了其在电路分析中的应用。在本文中，我们做出一个关键观察：即使LLM生成的RTL在功能上不完美，合成的网表仍保留了强烈指示预期功能的结构模式。基于这一见解，我们提出了一种成本效益高的数据增强和训练框架，系统地利用不完美的LLM生成RTL作为网表表示学习的训练数据，形成从自动化代码生成到下游任务的端到端流程。我们在电路功能理解任务上进行了评估，包括子电路边界识别和组件分类，在不同规模的基准上进行测试，将任务范围从操作级扩展到IP级。评估表明，训练在我们噪声合成语料库上的模型能够很好地泛化到真实世界网表，匹配或甚至超越了训练在稀缺高质量数据上的方法，并有效打破了电路表示学习中的数据瓶颈。
英文摘要：
Learning effective netlist representations is fundamentally constrained by the scarcity of labeled datasets, as real designs are protected by Intellectual Property (IP) and costly to annotate. Existing work therefore focuses on small-scale circuits with clean labels, limiting scalability to realistic designs. Meanwhile, Large Language Models (LLMs) can generate Register-Transfer-Level (RTL) at scale, but their functional incorrectness has hindered their use in circuit analysis. In this work, we make a key observation: even when LLM-Generated RTL is functionally imperfect, the synthesized netlists still preserve structural patterns that are strongly indicative of the intended functionality. Building on this insight, we propose a cost-effective data augmentation and training framework that systematically exploits imperfect LLM-Generated RTL as training data for netlist representation learning, forming an end-to-end pipeline from automated code generation to downstream tasks. We conduct evaluations on circuit functional understanding tasks, including sub-circuit boundary identification and component classification, across benchmarks of increasing scales, extending the task scope from operator-level to IP-level. The evaluations demonstrate that models trained on our noisy synthetic corpus generalize well to real-world netlists, matching or even surpassing methods trained on scarce high-quality data and effectively breaking the data bottleneck in circuit representation learning.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
