基于机器学习的智能电路设计与实现
Intelligent Circuit Design and Implementation with Machine Learning
摘要：
EDA技术的停滞源于知识重用不足。在实践中，可能需要从头开始重复构建非常相似的模拟或优化结果。这促使我研究如何通过机器学习（ML）将更多的"智能"引入EDA，ML基于先前的数据探索设计流程中的复杂相关性。除了设计时间，我还提出了ML解决方案，通过在运行时辅助电路管理来提高IC性能。在这篇论文中，我提出了多个快速而准确的ML模型，涵盖了广泛的芯片设计阶段，从寄存器传输级（RTL）的签署，解决主要的芯片设计问题的电源，时序，互连，IR下降，可布线性和设计流程调整。针对RTL阶段，我提出了APOLLO，一个全自动的电源建模框架。该算法通过提取功率相关性最强的信号，建立了精确的单周期功率模型。该模型可以进一步在芯片上实现，以前所未有的低硬件成本进行运行时电源管理。针对门级网表，我提出了Net2的早期估计后放置线长。它进一步实现了更准确的时序分析，而无需实际的物理设计信息。针对电路布局，我提出了早期可布线性预测的RouteNet。作为第一个基于深度学习的可布线性估计器，它提出的一些特征提取和模型设计原则被后来的工作广泛采用。我还介绍了用于快速IR压降估计的PowerNet。它利用定制的CNN架构捕获关于功率分布的空间和时间信息。最后，除了针对一个单一的设计步骤，我提出了FIST有效地调整设计流程参数在逻辑综合和物理设计。
英文摘要：
The stagnation of EDA technologies roots from insufficient knowledge reuse. In practice, very similar simulation or optimization results may need to be repeatedly constructed from scratch. This motivates my research on introducing more 'intelligence' to EDA with machine learning (ML), which explores complex correlations in design flows based on prior data. Besides design time, I also propose ML solutions to boost IC performance by assisting the circuit management at runtime. In this dissertation, I present multiple fast yet accurate ML models covering a wide range of chip design stages from the register-transfer level (RTL) to sign-off, solving primary chip-design problems about power, timing, interconnect, IR drop, routability, and design flow tuning. Targeting the RTL stage, I present APOLLO, a fully automated power modeling framework. It constructs an accurate per-cycle power model by extracting the most power-correlated signals. The model can be further implemented on chip for runtime power management with unprecedented low hardware costs. Targeting gate-level netlist, I present Net2 for early estimations on post-placement wirelength. It further enables more accurate timing analysis without actual physical design information. Targeting circuit layout, I present RouteNet for early routability prediction. As the first deep learning-based routability estimator, some feature-extraction and model-design principles proposed in it are widely adopted by later works. I also present PowerNet for fast IR drop estimation. It captures spatial and temporal information about power distribution with a customized CNN architecture. Last, besides targeting a single design step, I present FIST to efficiently tune design flow parameters during both logic synthesis and physical design.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
