一种基于逻辑复用的多字节乘法器设计用于低功耗向量计算
A Logic-Reuse Approach to Nibble-based Multiplier Design for Low Power Vector Computing
AI总结：
本文提出了一种基于逻辑复用的多字节乘法器设计，通过预计算和复用技术实现低功耗、高效率的向量计算。
摘要：
向量乘法是AI加速中的基本运算，负责卷积任务中超过85%的计算负载。尽管必要，这些运算是现代数据路径设计中面积、功率和延迟的主要驱动因素。传统乘法器架构往往在延迟和复杂性之间做出妥协：高速数组乘法器需要大量功率，而顺序设计在效率上牺牲了吞吐量。本文提出了一种预计算-复用多字节乘法器架构，通过将乘法重新表述为可重用的多字节级预计算值的结构化组合来弥合这一差距。所提出的设计将每个操作数视为独立的低精度元素，将其分解为固定宽度的多字节，并使用紧凑的移位加法逻辑生成广播操作数的缩放倍数。通过将宽查找表和多路复用器替换为基于逻辑的预计算和常规累积，该架构将周期复杂度与门延迟解耦。该设计在两个确定性周期内完成每个8位乘法，具有短关键路径，能够高效扩展到向量通道，并显著减少面积和能耗。在TSMC 28 nm技术下，RTL实现显示与移位加法相比，面积减少了1.69倍，能耗提高了1.63倍；在128位规模下，与基于查找表的数组乘法器相比，面积节省了近2.6倍，能耗节省了2.7倍。
英文摘要：
Vector multiplication is a fundamental operation for AI acceleration, responsible for over 85% of computational load in convolution tasks. While essential, these operations are primary drivers of area, power, and delay in modern datapath designs. Conventional multiplier architectures often force a compromise between latency and complexity: high-speed array multipliers demand significant power, whereas sequential designs offer efficiency at the cost of throughput. This paper presents a precompute-reuse nibble multiplier architecture that bridges this gap by reformulating multiplication as a structured composition of reusable nibble-level precomputed values. The proposed design treats each operand as an independent low-precision element, decomposes it into fixed-width nibbles, and generates scaled multiples of a broadcast operand using compact shift-add logic. By replacing wide lookup tables and multiway multiplexers with logic-based precomputation and regular accumulation, the architecture decouples cycle complexity from gate delay. The design completes each 8-bit multiplication in two deterministic cycles with a short critical path, scales efficiently across vector lanes, and significantly reduces area and energy consumption. RTL implementations synthesized in TSMC 28 nm technology demonstrate up to 1.69x area reduction and 1.63x power improvement over shift-add, and nearly 2.6x area and 2.7x power savings compared to LUT-based array multipliers at 128 bit scale.
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