Wildcat：面向教育的RISC-V微处理器
Wildcat: Educational RISC-V Microprocessors
AI总结：
本文提出更简单的三级流水线更适合RISC-V教学和嵌入式实现，因更长流水线会因转发多路选择器变宽而降低时钟频率，并通过FPGA和ASIC实验验证。
摘要：
在计算机体系结构课程中，我们通常使用五级流水线来教授RISC处理器，而忽略了其他组织结构。这种设计选择源于1980年代的技术，如今可能并非最优，而且肯定不是最易于教学的流水线。本文考察了更简单的RISC处理器流水线组织结构，这些结构适合教学目的以及在FPGA和ASIC中实现嵌入式处理器。我们分析了在FPGA中实现的各种设计的资源成本和最大时钟频率，以时钟频率作为性能代理。此外，我们使用开源SkyWater130工艺综合的ASIC设计验证了这些结果。与常识相反，更长的流水线（最多5级）并不一定总能提高最大时钟频率。在两个FPGA和一个ASIC实现中，我们发现四级或五级流水线比三级实现导致更慢的时钟频率。原因是执行阶段中转发多路选择器的宽度随着流水线变长而增加，而该选择器位于关键路径上。我们还论证了三级流水线组织结构更适合教授微处理器的流水线组织。
英文摘要：
In computer architecture courses, we usually teach RISC processors using a five-stage pipeline, neglecting alternative organizations. This design choice, rooted in the 1980s technology, may not be optimal today, and it is certainly not the easiest pipeline for education. This paper examines more straightforward pipeline organizations for RISC processors that are suitable for educational purposes and for implementing embedded processors in FPGAs and ASICs. We analyze resource costs and maximum clock frequency of various designs implemented in an FPGA, using clock frequency as a performance proxy. Additionally, we validate these results with ASIC designs synthesized using the open-source SkyWater130 process. Contradictory to common wisdom, a longer pipeline (up to 5 stages) does not necessarily always increase the maximum clock frequency. In two FPGA and one ASIC implementation, we discovered that a four- or five-stage pipeline leads to a slower clock frequency than a three-stage implementation. The reason is that the width of the forwarding multiplexer in the execution stage increases with longer pipelines, which is on the critical path. We also argue that a 3-stage pipeline organization is more adequate for teaching a pipeline organization of a microprocessor.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
