面向RISC-V ISA扩展的加速微内核多层编译器后端
A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions
AI总结：
本文提出一种多层编译器后端设计，通过渐进式lowering和结构化IR上的增量寄存器分配，为带硬件循环与流式寄存器的RISC-V加速器生成定制微内核，在关键DNN内核上实现高达90%的FPU利用率。
摘要：
高性能微内核必须充分利用当今多样且专用的硬件，才能为深度神经网络（DNN）提供峰值性能。虽然许多编译器（如MLIR、TVM、OpenXLA）提供了面向DNN的高层优化，但性能关键的微内核仍被留给专用代码生成器或手写汇编来处理。尽管广泛采用的编译器（如LLVM、GCC）提供了经过调优的后端，但它们以CPU为中心的输入抽象、非结构化中间表示（IR）以及通用型尽力而为的设计，抑制了面向创新硬件的定制化代码生成。我们认为，现在是时候拓宽经典的沙漏型后端，并在一组多样化的结构化抽象上采用渐进式 lowering，从而将领域专用代码生成引入编译器后端。我们通过为一个基于RISC-V的加速器实现定制后端来演示这一概念，该加速器具有硬件循环和流式寄存器，并在与其定制ISA相匹配的抽象层次上利用硬件知识。我们在结构化IR上使用增量寄存器分配，同时摒弃经典的溢出启发式方法，并在关键DNN内核上展示了高达90%的浮点单元（FPU）利用率。通过打破后端沙漏模型，我们重新打开了从领域专用抽象到专用硬件的路径。
英文摘要：
High-performance micro-kernels must fully exploit today's diverse and specialized hardware to deliver peak performance to DNNs. While higher-level optimizations for DNNs are offered by numerous compilers (e.g., MLIR, TVM, OpenXLA), performance-critical micro-kernels are left to specialized code generators or handwritten assembly. Even though widely-adopted compilers (e.g., LLVM, GCC) offer tuned backends, their CPU-focused input abstraction, unstructured IR, and general-purpose best-effort design inhibit tailored code generation for innovative hardware. We think it is time to widen the classical hourglass backend and embrace progressive lowering across a diverse set of structured abstractions to bring domain-specific code generation to compiler backends. We demonstrate this concept by implementing a custom backend for a RISC-V-based accelerator with hardware loops and streaming registers, leveraging knowledge about the hardware at levels of abstraction that match its custom ISA. We use incremental register allocation over structured IRs, while dropping classical spilling heuristics, and show up to 90% FPU utilization across key DNN kernels. By breaking the backend hourglass model, we reopen the path from domain-specific abstractions to specialized hardware.
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