Axon：一种采用片上 im2col 以改进 GeMM 和 Conv 运算运行时间与能效的新型脉动阵列架构
Axon: A novel systolic array architecture for improved run time and energy efficient GeMM and Conv operation with on-chip im2col
AI总结：
本文提出 Axon 新型脉动阵列数据编排架构，通过主对角线馈入与双向传播降低 GeMM 延迟，并以简单片上硬件支持 im2col，在低面积、功耗开销下提升 Conv 吞吐量与推理能效。
摘要：
通用矩阵乘法（GeMM）几乎是所有 AI 应用中的核心运算。基于脉动阵列（SA）的架构凭借其速度和能效，作为 GeMM 硬件加速器展现出巨大前景。遗憾的是，由于操作数通过流水线锁存器进行单向传播，SA 在填充操作数时会产生线性延迟。在本工作中，我们提出一种新型的阵列内数据编排技术：使数据能够沿主对角线馈入，随后进行双向传播。这以极小的硬件开销将运行时间最多提升 2 倍。此外，所提出的数据编排能够借助简单的硬件支持实现卷积降维（即 im2col），从而充分利用输入特征图的复用机会，并显著降低片外存储器流量；在 YOLOv3 和 RESNET50 工作负载上，平均带来 1.2 倍吞吐量提升和 2.17 倍推理能耗降低。相比之下，由于数据偏斜，传统数据编排若要在硬件中实现 im2col，则需要更复杂的硬件和控制信号。我们使用 ASAP 7nm PDK，对基于新型编排和传统编排的 16×16 脉动阵列进行了综合与布局布线，发现所提方法仅产生 0.211% 的面积开销和 1.6% 的功耗开销。
英文摘要：
General matrix multiplication (GeMM) is a core operation in virtually all AI applications. Systolic array (SA) based architectures have shown great promise as GeMM hardware accelerators thanks to their speed and energy efficiency. Unfortunately, SAs incur a linear delay in filling the operands, due to unidirectional propagation via pipeline latches. In this work, we propose a novel in-array data orchestration technique in SAs where we enable data feeding on the principal diagonal followed by bi-directional propagation. This improves the runtime by up to 2X at minimal hardware overhead. In addition, the proposed data orchestration enables convolution lowering (known as im2col) using a simple hardware support to fully exploit input feature map reuse opportunity and significantly lower the off-chip memory traffic resulting in 1.2X throughput improvement and 2.17X inference energy reduction during YOLOv3 and RESNET50 workload on average. In contrast, conventional data orchestration would require more elaborate hardware and control signals to implement im2col in hardware because of the data skew. We have synthesized and conducted place and route for 16X16 systolic arrays based on the novel and conventional orchestrations using ASAP 7nm PDK and found that our proposed approach results in 0.211% area and 1.6% power overheads.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
