HPR-Mul：一种基于近似计算的面积与高能效高精度冗余乘法器
HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate Computing
AI总结：
针对TMR乘法器面积能耗开销大且表决器易受软错误影响的问题，提出基于近似计算的HPR-Mul，利用全精度与降精度模块及公式化简单表决器，显著降低面积、功耗并提升容错能力。
摘要：
对于要求更高可靠性水平的关键应用，通常采用三模冗余（TMR）方案来实现容错算术单元。然而，该方法会带来显著的面积以及功耗/能量开销。此外，典型 TMR 设计中基于多数表决的表决器对软错误和三重化模块的设计多样性高度敏感，TMR 模块输出之间的微小差异便可能导致错误。不过，部署在关键系统中的大量应用本身具有错误弹性，即在具备给定可靠性水平的同时，能够容忍其输出中的某些不精确结果。本文提出一种高精度冗余乘法器（HPR-Mul），它依托近似计算原理，以实现更高的能效和更低的面积，并解决典型 TMR 方案的上述挑战，同时保持所需的可靠性水平。HPR-Mul 由一个全精度（FP）乘法器和两个降精度（RP）乘法器，以及一个用于确定输出的简单表决器组成。不同于现有最先进的降精度冗余乘法器（RPR-Mul）需要复杂表决器，所提出的 HPR-Mul 的表决器基于数学公式设计，因而结构更简单。此外，我们将 FP 乘法器的中间信号用作 RP 乘法器的输入，这显著提高了 HPR-Mul 的精度。所提出 HPR-Mul 的效率在 15-nm FinFET 工艺中进行了评估，结果表明，与典型的基于 TMR 的乘法器相比，其功耗和面积分别降低高达 70% 和 69%。此外，HPR-Mul 通过实现高达 84% 的更高软错误容忍度，优于现有最先进的 RPR-Mul。
英文摘要：
For critical applications that require a higher level of reliability, the Triple Modular Redundancy (TMR) scheme is usually employed to implement fault-tolerant arithmetic units. However, this method imposes a significant area and power/energy overhead. Also, the majority-based voter in the typical TMR designs is highly sensitive to soft errors and the design diversity of the triplicated module, which may result in an error for a small difference between the output of the TMR modules. However, a wide range of applications deployed in critical systems are inherently error-resilient, i.e., they can tolerate some inexact results at their output while having a given level of reliability. In this paper, we propose a High Precision Redundancy Multiplier (HPR-Mul) that relies on the principles of approximate computing to achieve higher energy efficiency and lower area, as well as resolve the aforementioned challenges of the typical TMR schemes, while retaining the required level of reliability. The HPR-Mul is composed of full precision (FP) and two reduced precision (RP) multipliers, along with a simple voter to determine the output. Unlike the state-of-the-art Reduced Precision Redundancy multipliers (RPR-Mul) that require a complex voter, the voter of the proposed HPR-Mul is designed based on mathematical formulas resulting in a simpler structure. Furthermore, we use the intermediate signals of the FP multiplier as the inputs of the RP multipliers, which significantly enhance the accuracy of the HPR-Mul. The efficiency of the proposed HPR-Mul is evaluated in a 15-nm FinFET technology, where the results show up to 70% and 69% lower power consumption and area, respectively, compared to the typical TMR-based multipliers. Also, the HPR-Mul outperforms the state-of-the-art RPR-Mul by achieving up to 84% higher soft error tolerance.
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