混合模块化冗余：探索RISC-V多核计算集群中的模块化冗余方法以实现太空中的可靠处理
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space
AI总结：
本文提出混合模块化冗余（HMR）方法，在RISC-V多核集群中实现灵活的按需双核/三核锁步冗余与拆分锁能力，并结合软硬件两种恢复机制，以较低面积开销实现太空计算中可精细调节的可靠性与性能权衡。
摘要：
航天器和卫星等太空信息物理系统（S-CPS）高度依赖机载计算机的可靠性来保证任务成功。仅依赖抗辐射加固技术成本极其高昂，而在系统内部引入模块化冗余所需的不灵活的架构和微架构修改会导致显著的面积增加和性能下降。为了减轻传统抗辐射加固和模块化冗余方法的开销，我们提出了一种新颖的混合模块化冗余（HMR）方法，这是一种冗余方案，其特点是由RISC-V处理器组成的集群，具有灵活的按需双核和三核锁步分组计算核心的能力，并具备运行时拆分锁（split-lock）能力。此外，我们提出了两种恢复方法，基于软件的和基于硬件的，在性能和面积开销之间进行权衡。在430 MHz运行频率下，我们的容错集群在配置为非冗余模式时，在矩阵乘法基准测试上实现高达1160 MOPS，在双核和三核模式下分别实现617和414 MOPS。三核模式下基于软件的恢复需要363个时钟周期，占用0.612 mm2，相对于非冗余的12核RISC-V集群仅增加1.3%的面积开销。作为一种高性能替代方案，一种新的基于硬件的方法可在仅24个时钟周期内实现快速故障恢复，占用0.660 mm2，即相对于基线非冗余RISC-V集群约9.4%的面积开销。该集群还增强了拆分锁能力，可以以最小的性能损失进入其中一种冗余模式，允许执行任务关键型或性能型代码段，进入和退出的开销小于400个时钟周期。所提出的系统是首个在基于开源RISC-V的计算设备上集成这些功能的设计，实现了可精细调节的可靠性与性能之间的权衡。
英文摘要：
Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying solely on radiation-hardened technologies is extremely expensive, and developing inflexible architectural and microarchitectural modifications to introduce modular redundancy within a system leads to significant area increase and performance degradation. To mitigate the overheads of traditional radiation hardening and modular redundancy approaches, we present a novel Hybrid Modular Redundancy (HMR) approach, a redundancy scheme that features a cluster of RISC-V processors with a flexible on-demand dual-core and triple-core lockstep grouping of computing cores with runtime split-lock capabilities. Further, we propose two recovery approaches, software-based and hardware-based, trading off performance and area overhead. Running at 430 MHz, our fault-tolerant cluster achieves up to 1160 MOPS on a matrix multiplication benchmark when configured in non-redundant mode and 617 and 414 MOPS in dual and triple mode, respectively. A software-based recovery in triple mode requires 363 clock cycles and occupies 0.612 mm2, representing a 1.3% area overhead over a non-redundant 12-core RISC-V cluster. As a high-performance alternative, a new hardware-based method provides rapid fault recovery in just 24 clock cycles and occupies 0.660 mm2, namely ~9.4% area overhead over the baseline non-redundant RISC-V cluster. The cluster is also enhanced with split-lock capabilities to enter one of the redundant modes with minimum performance loss, allowing execution of a mission-critical or a performance section, with <400 clock cycles overhead for entry and exit. The proposed system is the first to integrate these functionalities on an open-source RISC-V-based compute device, enabling finely tunable reliability vs. performance trade-offs.
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