CraftRTL：面向Verilog代码模型的高质量合成数据生成，采用构造即正确的非文本表示与定向代码修复
CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair
AI总结：
本文提出CraftRTL方法，通过构造即正确的非文本表示数据和自动化定向代码修复数据生成，微调Starcoder2-15B，在三个Verilog基准上显著超越先前最优结果。
摘要：
尽管使用大语言模型进行代码生成已取得显著进展，但挑战依然存在，尤其是在Verilog等硬件描述语言方面。本文首先对基于先前方法合成数据微调后的LLM在Verilog编码上的表现进行了分析。我们识别出两个主要问题：处理非文本表示（卡诺图、状态转移图和波形图）的困难，以及训练过程中模型随机出现“轻微”错误所导致的显著不稳定性。为解决这些局限性，我们通过创建针对非文本表示的构造即正确数据来增强数据管理。此外，我们引入了一个自动化框架，该框架从多个模型检查点生成错误报告，并将这些错误注入开源代码中以创建定向代码修复数据。我们微调后的Starcoder2-15B在VerilogEval-Machine、VerilogEval-Human和RTLLM上的pass@1指标分别比先前最先进结果高出3.8%、10.9%和6.6%。
英文摘要：
Despite the significant progress made in code generation with large language models, challenges persist, especially with hardware description languages such as Verilog. This paper first presents an analysis of fine-tuned LLMs on Verilog coding, with synthetic data from prior methods. We identify two main issues: difficulties in handling non-textual representations (Karnaugh maps, state-transition diagrams and waveforms) and significant variability during training with models randomly making "minor" mistakes. To address these limitations, we enhance data curation by creating correct-by-construction data targeting non-textual representations. Additionally, we introduce an automated framework that generates error reports from various model checkpoints and injects these errors into open-source code to create targeted code repair data. Our fine-tuned Starcoder2-15B outperforms prior state-of-the-art results by 3.8%, 10.9%, 6.6% for pass@1 on VerilogEval-Machine, VerilogEval-Human, and RTLLM.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
