Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所）；University of Chinese Academy of Sciences（中国科学院大学）；Nanjing University（南京大学）；Shanghai University（上海大学）；Zhejiang University（浙江大学）；Shanghai Innovation Center for Processor Technologies（上海处理器技术创新中心）；FuDan University（复旦大学）；Hangzhou Institute for Advanced Study, University of Chinese Academy of Sciences（中国科学院大学杭州高等研究院）；University of Illinois at Urbana Champaign（伊利诺伊大学厄巴纳-香槟分校）；Shanghai Jiao Tong University（上海交通大学）；Zhejiang Lab（之江实验室）
Recent advances in large language models have demonstrated their potential for automated generation of hardware description language (HDL) code from high-level prompts. Researchers have utilized fine-tuning to enhance the ability of these large language models (LLMs) in the field of Chip Design. However, the lack of Verilog data hinders further improvement in the quality of Verilog generation by LLMs. Additionally, the absence of a Verilog and Electronic Design Automation (EDA) script data augmentation framework significantly increases the time required to prepare the training dataset for LLM trainers. This paper proposes an automated design-data augmentation framework, which generates high-volume and high-quality natural language aligned with Verilog and EDA scripts. For Verilog generation, it translates Verilog files to an abstract syntax tree and then maps nodes to natural language with a predefined template. For Verilog repair, it uses predefined rules to generate the wrong verilog file and then pairs EDA Tool feedback with the right and wrong verilog file. For EDA Script generation, it uses existing LLM(GPT-3.5) to obtain the description of the Script. To evaluate the effectiveness of our data augmentation method, we finetune Llama2-13B and Llama2-7B models using the dataset generated by our augmentation framework. The results demonstrate a significant improvement in the Verilog generation tasks with LLMs. Moreover, the accuracy of Verilog generation surpasses that of the current state-of-the-art open-source Verilog generation model, increasing from 58.8% to 70.6% with the same benchmark. Our 13B model (ChipGPT-FT) has a pass rate improvement compared with GPT-3.5 in Verilog generation and outperforms in EDA script (i.e., SiliconCompiler) generation with only 200 EDA script data.
ChipGPT: How far are we from natural language hardware design
State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, China（处理器国家重点实验室，计算技术研究所，中国科学院，中国）；University of Chinese Academy of Sciences（中国科学院大学）；School of Information Science and Technology, ShanghaiTech University, China（信息科学与技术学院，上海科技大学，中国）
Align Generative Artificial Intelligence with Human Preferences: A Novel Large Language Model Fine-Tuning Method for Online Review Management
Department of Information Systems and Operations Management, The University of Texas at Arlington（信息系统与运营管理系，德克萨斯大学阿灵顿分校）；Department of Management Information Systems, University of Arizona（管理信息学系，亚利桑那大学）
Conversation AI Dialog for Medicare powered by Finetuning and Retrieval Augmented Generation
University of Florida（佛罗里达大学）；National Institute of Technology Calicut（卡利卡特国家理工学院）；SRM, Chennai（SRM大学（金奈））；University of Cincinnati（辛辛那提大学）；Dartmouth College（达特茅斯学院）；Arizona State University（亚利桑那州立大学）
MiniConGTS: A Near Ultimate Minimalist Contrastive Grid Tagging Scheme for Aspect Sentiment Triplet Extraction
Shanghai Artificial Intelligence Laboratory（上海人工智能实验室）；Academy of Engineering and Technology, Fudan University（复旦大学工程与技术学院）；Shanghai Jiao Tong University（上海交通大学）；School of Information Science and Technology, Fudan University（复旦大学信息科学与技术学院）
