fence.t.s：通过ISA支持的时间分区关闭高性能乱序核心中的时序信道
fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning
AI总结：
针对RISC-V中fence.t指令在超标量乱序核心中关闭时序信道的挑战，提出软件支持的fence.t.s方案，复用现有机制，以极低硬件成本和1.0%性能影响为OpenC910核心提供完整时序信道防护。
摘要：
微体系结构时序信道会利用本应隔离的安全域之间的信息泄露，绕过操作系统的安全边界。这类信道由对共享微体系结构状态的争用导致。在RISC-V指令集中，时间隔离指令fence.t（时间栅障指令）被提出用于关闭时序信道，它为操作系统提供了在简单顺序核心中以低成本对微体系结构状态进行时间分区的手段。本研究探讨了fence.t在具备大规模、普遍存在的微体系结构状态的超标量乱序核心中面临的挑战。为克服这些挑战，我们提出了一种新型软件支持的时间栅障fence.t.s，它复用现有机制并支持高级微体系结构特性，能够以可忽略的硬件成本和1.0%的极小性能影响，为典型乱序核心OpenC910提供完整的时序信道防护。
英文摘要：
Microarchitectural timing channels exploit information leakage between security domains that should be isolated, bypassing the operating system's security boundaries. These channels result from contention for shared microarchitectural state. In the RISC-V instruction set, the temporal fence instruction (fence.t) was proposed to close timing channels by providing an operating system with the means to temporally partition microarchitectural state inexpensively in simple in-order cores. This work explores challenges with fence.t in superscalar out-of-order cores featuring large and pervasive microarchitectural state. To overcome these challenges, we propose a novel SW-supported temporal fence (fence.t.s), which reuses existing mechanisms and supports advanced microarchitectural features, enabling full timing channel protection of an exemplary out-of-order core (OpenC910) at negligible hardware costs and a minimal performance impact of 1.0 %.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
