HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices
School of Computer Science and Engineering, Beihang University（北京航空航天大学计算机科学与工程学院）；School of Integrated Circuits and Engineering, Beihang University（北京航空航天大学集成电路与工程学院）
Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu
Graph Neural Networks (GNNs) are becoming increasingly popular for graph-based learning tasks such as point cloud processing due to their state-of-the-art (SOTA) performance. Nevertheless, the research community has primarily focused on improving model expressiveness, lacking consideration of how to design efficient GNN models for edge scenarios with real-time requirements and limited resources. Examining existing GNN models reveals varied execution across platforms and frequent Out-Of-Memory (OOM) problems, highlighting the need for hardware-aware GNN design. To address this challenge, this work proposes a novel hardware-aware graph neural architecture search framework tailored for resource constraint edge devices, namely HGNAS. To achieve hardware awareness, HGNAS integrates an efficient GNN hardware performance predictor that evaluates the latency and peak memory usage of GNNs in milliseconds. Meanwhile, we study GNN memory usage during inference and offer a peak memory estimation method, enhancing the robustness of architecture evaluations when combined with predictor outcomes. Furthermore, HGNAS constructs a fine-grained design space to enable the exploration of extreme performance architectures by decoupling the GNN paradigm. In addition, the multi-stage hierarchical search strategy is leveraged to facilitate the navigation of huge candidates, which can reduce the single search time to a few GPU hours. To the best of our knowledge, HGNAS is the first automated GNN design framework for edge devices, and also the first work to achieve hardware awareness of GNNs across different platforms. Extensive experiments across various applications and edge devices have proven the superiority of HGNAS. It can achieve up to a 10.6x speedup and an 82.5% peak memory reduction with negligible accuracy loss compared to DGCNN on ModelNet40.
Hardware-Aware Neural Feature Extraction for Resource-Constrained Devices
Department of Electronics, Information and Bioengineering (DEIB), Politecnico di Milano（电子、信息与生物工程系（DEIB），米兰理工学院）；Smart Eyewear Lab, EssilorLuxottica（智能眼镜实验室，EssilorLuxottica）
On Hardware-Aware Design and Optimization of Edge Intelligence
School of Computer Science and Engineering, Nanyang Technological University, Singapore（南洋理工大学计算机科学与工程学院）；HP-NTU Digital Manufacturing Corporate Lab, Nanyang Technological University, Singapore（南洋理工大学HP-NTU数字制造企业实验室）；Department of Computer Science, Norwegian University of Science and Technology, Norway（挪威技术大学计算机科学系）；HP Inc., Palo Alto, California, USA（惠普公司）
HW-GPT-Bench: Hardware-Aware Architecture Benchmark for Language Models
University of Freiburg（弗赖堡大学）；Bosch Center for Artificial Intelligence (BCAI)（博世人工智能中心）；ELLIS Institute Tübingen（埃利斯研究所蒂宾根分所）；ScaDS.AI, Leipzig（莱比锡ScaDS.AI）
Towards Cardiac Intervention Assistance: Hardware-aware Neural Architecture Exploration for Real-Time 3D Cardiac Cine MRI Segmentation
University of Notre Dame（圣母大学）；Guangdong Cardiovascular Institute（广东省心血管病研究所）；Guangdong Provincial People’s Hospital（广东省人民医院）；Boston Children’s Hospital（波士顿儿童医院）；Harvard Medical School（哈佛医学院）；University of Pittsburgh（匹兹堡大学）
Intrusion Detection on Resource-Constrained IoT Devices with Hardware-Aware ML and DL
Faculty of Sciences, Lebanese University（科学学院，黎巴嫩大学）；DITEN, University of Genova（DITEN，热那亚大学）；IMT Atlantique, Lab-STICC UMR CNRS 6285（IMT Atlantique，Lab-STICC UMR CNRS 6285）；School of Arts and Sciences, Lebanese American University（艺术与科学学院，黎巴嫩美国大学）
MDQEC-QAS: Meta-Decoding for Quantum Error Correction with Hardware-Aware VQC Search and Confidence-Gated Recovery
Department of Physics, Indian Institute of Technology (BHU)（印度理工学院（BHU）物理系）；eBRAIN Lab, Division of Engineering, New York University Abu Dhabi (NYUAD)（纽约大学阿布扎克分校（NYUAD）工程学院eBRAIN实验室）；Center for Quantum and Topological Systems (CQTS), NYUAD Research Institute, NYUAD（纽约大学阿布扎克分校（NYUAD）量子与拓扑系统中心（CQTS））
NeuroNAS: Enhancing Efficiency of Neuromorphic In-Memory Computing for Intelligent Mobile Agents through Hardware-Aware Spiking Neural Architecture Search
From Bits to Chips: An LLM-based Hardware-Aware Quantization Agent for Streamlined Deployment of LLMs
The University of Arizona（亚利桑那大学）；Clemson University（克莱姆森大学）；University of Georgia（佐治亚大学）；The University of Tulsa（塔尔萨大学）；Northeastern University（东北大学）；Western Digital Corporation（西部数据公司）
Hardware-aware Training Techniques for Improving Robustness of Ex-Situ Neural Network Transfer onto Passive TiO2 ReRAM Crossbars
IT (Institut Interdisciplinaire d’Innovation Technologique)（跨学科技术创新研究所）；Université de Sherbrooke（舍布鲁克大学）；Institute of Electronics, Microelectronics and Nanotechnology (IEMN), Université de Lille（里尔大学电子、微电子与纳米技术研究所）
PQuantML: A Tool for End-to-End Hardware-aware Model Compression
European Center for Nuclear Research (CERN)（欧洲核子研究中心）；Purdue University（普渡大学）；California Institute of Technology（加州理工学院）；University of Padova（帕多瓦大学）；Physikalisches Institut, Heidelberg University（海德堡大学物理研究所）；SLAC National Accelerator Laboratory（SLAC国家加速器实验室）；Institute of Physics Belgrade（贝尔格莱德物理研究所）
SigmaQuant: Hardware-Aware Heterogeneous Quantization Method for Edge DNN Inference
Embedded Systems Laboratory (ESL), EPFL, Switzerland（嵌入式系统实验室（ESL），EPFL，瑞士）；University of Applied Sciences and Arts Western Switzerland (HES-SO), Switzerland（应用科学与艺术西瑞士大学（HES-SO），瑞士）
