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arXiv 2407.12640quant-phcs.ETcs.LG
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面向单核与多核架构高效执行的量子电路特征分析

Profiling quantum circuits for their efficient execution on single- and multi-core architectures

Universitat Politècnica de Catalunya（加泰罗尼亚理工大学）

Medina Bandic, Pablo le Henaff, Anabel Ovide, Pau Escofet, Sahar Ben Rached, Santiago Rodrigo, Hans van Someren, Sergi Abadal, Eduard Alarcon, Carmen G. Almudever, Sebastian Feld

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AI总结：

本研究首次引入基于图论的度量指标，对量子电路进行严格分析，揭示电路属性与映射性能的联系，并强调多核架构的潜力，以助力性能预测和基准测试集定义。

摘要：

专用量子计算机为处理经典计算机难以解决的问题提供了最高效的手段。实现这些架构需要深入理解量子电路的特性及其与量子设备上执行结果之间的关系。我们的研究首次尝试通过引入基于图论的度量指标（这些指标从量子比特交互图和门依赖图中提取）以及描述电路本身的常规参数，对量子电路进行严格的检验。该方法有助于对量子电路进行全面分析和聚类。此外，它揭示了根植于量子比特交互图和门依赖图的参数与量子电路映射性能指标之间的联系，这一发现在一系列既定的量子设备和映射配置中均成立。在各种设备配置中，我们特别强调模块化（即多核）量子计算架构，因为它们在量子设备可扩展性方面具有作为可行解决方案的巨大潜力。这项深入的分析将帮助我们：i) 识别影响量子电路映射性能指标的关键电路属性；ii) 针对相似电路结构预测其在特定芯片上的性能；iii) 为特定电路确定映射技术与硬件设置的优选组合；iv) 通过对结构相似的电路进行聚类来定义具有代表性的基准测试集。

英文摘要：

Application-specific quantum computers offer the most efficient means to tackle problems intractable by classical computers. Realizing these architectures necessitates a deep understanding of quantum circuit properties and their relationship to execution outcomes on quantum devices. Our study aims to perform for the first time a rigorous examination of quantum circuits by introducing graph theory-based metrics extracted from their qubit interaction graph and gate dependency graph alongside conventional parameters describing the circuit itself. This methodology facilitates a comprehensive analysis and clustering of quantum circuits. Furthermore, it uncovers a connection between parameters rooted in both qubit interaction and gate dependency graphs, and the performance metrics for quantum circuit mapping, across a range of established quantum device and mapping configurations. Among the various device configurations, we particularly emphasize modular (i.e., multi-core) quantum computing architectures due to their high potential as a viable solution for quantum device scalability. This thorough analysis will help us to: i) identify key attributes of quantum circuits that affect the quantum circuit mapping performance metrics; ii) predict the performance on a specific chip for similar circuit structures; iii) determine preferable combinations of mapping techniques and hardware setups for specific circuits; and iv) define representative benchmark sets by clustering similarly structured circuits.

机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。

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