表面码量子计算的低成本算法到执行框架
Low-cost algorithm-to-execution framework for surface-code quantum computing
- Center on Frontiers of Computing Studies, Peking University（前沿计算研究中心，北京大学）
- School of Computer Science, Peking University（计算机学院，北京大学）
机构由 AI 辅助整理，请以论文原文为准。
AI总结：
本文提出表面码量子计算的低成本算法到执行框架，通过依赖保留调度和可执行工作负载链接逻辑计算与容错执行，在基准测试中显著降低时空体积和路由延迟。
AI中文摘要：
在容错处理器上执行有用的量子算法，不仅需要从逻辑门到编码操作的映射：还必须确定空间组织、非克利福德资源供应和执行调度，同时将物理开销保持在实用限度内。尽管从逻辑电路到容错操作的理论层级已经确立，但这些实现选择通常被分别指定和优化。在此，我们为表面码量子计算开发了一个低成本的算法到执行框架。该框架从分层算法描述出发，构建保留依赖关系的逻辑调度和可执行工作负载，捕获逻辑交互、操作并行性和时间分辨的非克利福德需求，从而在可追踪的工作流程中将逻辑计算与表面码组织、资源态制备和容错执行联系起来。我们将该框架应用于七个算法家族的二十个基准电路，以及一个分层组成的应用规模椭圆曲线离散对数工作负载。即使逻辑资源数量相似的电路，物理成本也差异显著。在我们的直接旋转校准下，对于QAOA幅度放大工作负载，非克利福德实现选择相比全合成基线将时空体积减少了最多241.5倍。特定于电路的表面码布局降低了所有二十个基准的路由延迟估计；其中十三个还减少了时空体积，因为通信节省超过了增加的空间开销。这些结果表明，低成本的容错执行取决于计算调度和组织，而非仅取决于总体逻辑资源数量。
英文摘要：
The execution of useful quantum algorithms on fault-tolerant processors requires more than a mapping from logical gates to encoded operations: the spatial organization, non-Clifford resource supply, and execution schedule must also be determined while keeping physical overhead within practical limits. Although the theoretical hierarchy from logical circuits to fault-tolerant operations is well established, these implementation choices are often specified and optimized separately. Here we develop a low-cost algorithm-to-execution framework for surface-code quantum computing. From hierarchical algorithm descriptions, it constructs dependency-preserving logical schedules and an executable workload capturing logical interactions, operation parallelism, and time-resolved non-Clifford demand, thereby linking logical computation to surface-code organization, resource-state preparation, and fault-tolerant execution in a traceable workflow. We apply the framework to twenty benchmark circuits across seven algorithm families and a hierarchically composed application-scale elliptic-curve discrete-logarithm workload. Physical costs vary substantially even for circuits with similar logical resource counts. Under our direct-rotation calibration, non-Clifford implementation selection reduces space-time volume by up to 241.5 times versus an all-synthesis baseline for the QAOA amplitude-amplification workload. Circuit-specific surface-code layouts reduce routed-latency estimates for all twenty benchmarks; thirteen also reduce space-time volume because communication savings outweigh added spatial overhead. These results show that low-cost fault-tolerant execution depends on computation scheduling and organization, not aggregate logical resource counts alone.
