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arXiv 2405.13639cs.LG
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关于概率电路硬件高效推理的研究

On Hardware-efficient Inference in Probabilistic Circuits

Aalto University(阿尔托大学);ICTEAM UCLouvain(天主教鲁汶大学 ICTEAM 研究所)

Lingyun Yao, Martin Trapp, Jelin Leslin, Gaurav Singh, Peng Zhang, Karthekeyan Periasamy, Martin Andraud

AI总结:

本文提出首个针对概率电路的专用近似计算框架,利用“加法即整数”实现低分辨率对数计算,在自定义硬件上实现高达357倍和649倍的能量减少,且几乎无计算误差。

摘要:

概率电路(PCs)为在不确定性下执行嵌入式推理提供了一种有前景的途径。它们通过设计支持各种概率推理任务的高效且精确的计算。因此,概率电路的硬件高效计算对于边缘计算应用极具吸引力。由于概率电路中的计算基于概率值的算术运算,通常在对数域中执行以避免下溢。不幸的是,在硬件上执行对数运算成本高昂。因此,先前的工作专注于线性域中的计算,导致高分辨率和能量需求。这项工作提出了第一个专门针对概率电路的近似计算框架,允许低分辨率对数计算。我们利用“加法即整数”(Addition As Int)方法,实现具有简单硬件元件的线性概率电路计算。此外,我们提供了理论近似误差分析,并提出了一种误差补偿机制。实验上,我们的方法在自定义硬件上分别实现了高达357倍和649倍的能量减少,用于证据查询和最大后验(MAP)查询,且几乎没有计算误差。

英文摘要:

Probabilistic circuits (PCs) offer a promising avenue to perform embedded reasoning under uncertainty. They support efficient and exact computation of various probabilistic inference tasks by design. Hence, hardware-efficient computation of PCs is highly interesting for edge computing applications. As computations in PCs are based on arithmetic with probability values, they are typically performed in the log domain to avoid underflow. Unfortunately, performing the log operation on hardware is costly. Hence, prior work has focused on computations in the linear domain, resulting in high resolution and energy requirements. This work proposes the first dedicated approximate computing framework for PCs that allows for low-resolution logarithm computations. We leverage Addition As Int, resulting in linear PC computation with simple hardware elements. Further, we provide a theoretical approximation error analysis and present an error compensation mechanism. Empirically, our method obtains up to 357x and 649x energy reduction on custom hardware for evidence and MAP queries respectively with little or no computational error.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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