通过利用非结构化比特级稀疏性实现高效SRAM-PIM架构设计
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity
AI总结：
针对传统SRAM-PIM架构难以利用神经网络非结构化比特级稀疏性的问题，提出DB-PIM算法-架构协同设计框架，通过二进块稀疏模式、定制PIM宏单元等实现最高7.69倍加速与83.43%能耗节省。
摘要：
神经网络模型中的比特级稀疏性蕴含着巨大的未开发潜力。消除随机分布的零比特的冗余计算可显著提升计算效率。然而，传统数字SRAM-PIM（静态随机存取存储器-存内计算）架构受限于刚性的交叉阵列结构，难以有效利用这种非结构化稀疏性。为解决这一挑战，我们提出Dyadic Block PIM（DB-PIM，二进块存内计算），这是一种突破性的算法-架构协同设计框架。首先，我们提出了一种搭配独特稀疏模式（称为二进块DB）的算法，该模式保留非零比特的随机分布以维持精度，同时限制每个权重中这些比特的数量以提升规整性。在架构层面，我们开发了定制的PIM宏单元，包含二进块乘法单元（DBMU）和基于Canonical Signed Digit（CSD，规范有符号数字）的加法树，专门适配乘累加（MAC）运算。输入预处理单元（IPU）通过利用分块输入稀疏性进一步优化性能与效率。结果表明，我们提出的协同设计框架实现了最高7.69倍的显著加速和83.43%的能耗节省。
英文摘要：
Bit-level sparsity in neural network models harbors immense untapped potential. Eliminating redundant calculations of randomly distributed zero-bits significantly boosts computational efficiency. Yet, traditional digital SRAM-PIM architecture, limited by rigid crossbar architecture, struggles to effectively exploit this unstructured sparsity. To address this challenge, we propose Dyadic Block PIM (DB-PIM), a groundbreaking algorithm-architecture co-design framework. First, we propose an algorithm coupled with a distinctive sparsity pattern, termed a dyadic block (DB), that preserves the random distribution of non-zero bits to maintain accuracy while restricting the number of these bits in each weight to improve regularity. Architecturally, we develop a custom PIM macro that includes dyadic block multiplication units (DBMUs) and Canonical Signed Digit (CSD)-based adder trees, specifically tailored for Multiply-Accumulate (MAC) operations. An input pre-processing unit (IPU) further refines performance and efficiency by capitalizing on block-wise input sparsity. Results show that our proposed co-design framework achieves a remarkable speedup of up to 7.69x and energy savings of 83.43%.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
