Nvidia Hopper GPU架构的基准测试与剖析
Benchmarking and Dissecting the Nvidia Hopper GPU Architecture
AI总结：
本文首次对Nvidia Hopper GPU进行系统基准测试，通过对比Hopper、Ada和Ampere架构并剖析DPX指令集、分布式共享内存及FP8张量核心，揭示其微架构特性，为GPU优化与建模提供依据。
摘要：
图形处理单元（GPU）持续演进，以满足当代通用工作负载的计算需求，尤其是由采用深度学习技术的人工智能（AI）驱动的工作负载。已有大量研究致力于剖析不同GPU世代的微架构指标，这有助于研究人员理解硬件细节并利用这些细节优化GPU程序。然而，最新的Hopper GPU呈现出一系列新特性，包括支持FP8的新张量核心、DPX以及分布式共享内存。它们在性能和运行特性方面的细节仍然不为人知。在本研究中，我们提出了一项针对Hopper GPU的广泛基准测试研究。其目标是通过考察Nvidia GPU的新指令集架构（ISA）以及新CUDA API的使用，揭示其微架构的复杂细节。我们的方法涉及两个主要方面。首先，我们在三个最新的GPU架构（即Hopper、Ada和Ampere）之间进行常规的延迟和吞吐量对比基准测试。其次，我们深入讨论并对最新的Hopper特性进行基准测试，涵盖Hopper DPX动态规划（DP）指令集、分布式共享内存以及FP8张量核心的可用性。我们呈现的微基准测试结果提供了对Hopper架构引入的新型GPU AI功能单元和编程特性的更深入理解。这一新获得的理解预计将极大地促进GPU架构的软件优化和建模工作。据我们所知，本研究首次尝试揭开Hopper GPU独有的张量核心性能和编程指令集的神秘面纱。
英文摘要：
Graphics processing units (GPUs) are continually evolving to cater to the computational demands of contemporary general-purpose workloads, particularly those driven by artificial intelligence (AI) utilizing deep learning techniques. A substantial body of studies have been dedicated to dissecting the microarchitectural metrics characterizing diverse GPU generations, which helps researchers understand the hardware details and leverage them to optimize the GPU programs. However, the latest Hopper GPUs present a set of novel attributes, including new tensor cores supporting FP8, DPX, and distributed shared memory. Their details still remain mysterious in terms of performance and operational characteristics. In this research, we propose an extensive benchmarking study focused on the Hopper GPU. The objective is to unveil its microarchitectural intricacies through an examination of the new instruction-set architecture (ISA) of Nvidia GPUs and the utilization of new CUDA APIs. Our approach involves two main aspects. Firstly, we conduct conventional latency and throughput comparison benchmarks across the three most recent GPU architectures, namely Hopper, Ada, and Ampere. Secondly, we delve into a comprehensive discussion and benchmarking of the latest Hopper features, encompassing the Hopper DPX dynamic programming (DP) instruction set, distributed shared memory, and the availability of FP8 tensor cores. The microbenchmarking results we present offer a deeper understanding of the novel GPU AI function units and programming features introduced by the Hopper architecture. This newfound understanding is expected to greatly facilitate software optimization and modeling efforts for GPU architectures. To the best of our knowledge, this study makes the first attempt to demystify the tensor core performance and programming instruction sets unique to Hopper GPUs.
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