AI 中文总结
本文提出自动化指令编码综合框架，将指令布局视为约束槽分配问题，在NVIDIA SASS上验证，变长编码减少33%指令占用空间，定长编码减少16%解码器面积，并生成满足1.5 GHz的RTL。
AI 中文摘要
现代GPU内核日益加剧指令供给路径的压力，而固定指令容器可能留下大量占用空间冗余。本文提出一个自动化编码综合框架，将指令布局视为在经验证的指令形式字段规范上的约束槽分配问题。该公式将语义字段身份与物理位位置分离，并支持绑定、固定和自由放置约束，使其在重复解码字段未被公共格式契约冻结时适用。我们针对NVIDIA SASS实例化该框架：原始公共编码文本被规范化为机器可读规范，SASS反汇编器在3.78M条指令上与nvdisasm验证，作为开放基准发布，并使用CP-SAT综合用于定长和变长编码。在142个Blackwell内核输入上，变长综合将指令占用空间减少33%，在Ampere和Hopper上重新综合后也有类似减少；相同规范上的定长综合相对于由同一生成器和流程从NVIDIA观察到的128位布局生成的解码器，将解码器面积减少16%。生成的取指/解码RTL在TSMC 22 nm工艺下达到1.5 GHz，复制面积增量为GA100级芯片的0.12%；同节点SRAM比较显示，占用空间减少对应约9倍于该增加逻辑的指令SRAM位单元面积。
英文摘要
Modern GPU kernels increasingly stress the instruction supply path, while fixed instruction containers can leave substantial footprint slack. This paper presents an automated encoding-synthesis framework that treats instruction layout as a constrained slot-assignment problem over a validated instruction-form field specification. The formulation separates semantic field identity from physical bit positions and supports tied, pinned, and free placement constraints, making it applicable when recurring decoded fields are not frozen by a public format contract. We instantiate the framework for NVIDIA SASS: raw public encoding text is normalized into a machine-readable specification, a SASS disassembler is validated against nvdisasm on 3.78M instructions, released as an open benchmark, and CP-SAT synthesis is used for fixed-length and variable-length encodings. On 142 Blackwell kernel inputs, variable-length synthesis reduces instruction footprint by 33%, with comparable reductions after re-synthesis on Ampere and Hopper; fixed-length synthesis on the same specification reduces decoder area by 16% against a decoder generated from the NVIDIA-observed 128-bit layout by the same generator and flow. Generated fetch/decode RTL meets 1.5 GHz in TSMC 22 nm with a replicated area delta of 0.12% of a GA100-class die; a same-node SRAM comparison shows the footprint reduction corresponds to about 9x this added logic in instruction-SRAM bit-cell area.
Comments9 pages, 7 figures, 6 tables. Accepted at the IEEE International Conference on Computer Design (ICCD), 2026. Code: https://github.com/reoLantern/nvsass-disassembler
