Macro placement is a critical phase in chip design, which becomes more intricate when involving general rectilinear macros and layout areas. Furthermore, macro placement that incorporates human-like constraints, such as design hierarchy and peripheral bias, has the potential to significantly reduce the amount of additional manual labor required from designers. This study proposes a methodology that leverages an approach suggested by Google's Circuit Training (G-CT) to provide a learning-based macro placer that not only supports placing rectilinear cases, but also adheres to crucial human-like design principles. Our experimental results demonstrate the effectiveness of our framework in achieving power-performance-area (PPA) metrics and in obtaining placements of high quality, comparable to those produced with human intervention. Additionally, our methodology shows potential as a generalized model to address diverse macro shapes and layout areas.
Department of EECS, UC Berkeley, CA, USA（UC伯克利电子工程与计算机科学系）；SambaNova Systems Inc., Palo Alto, CA, USA（SambaNova Systems公司）；Computer Science Department, Stanford University, CA, USA（斯坦福大学计算机科学系）
University of Amsterdam（阿姆斯特丹大学）；Qualcomm AI Research（高通人工智能研究院）；QT Technologies Ireland Limited（QT技术爱尔兰有限公司）；QUALCOMM India Private Limited（高通印度私人有限公司）
Physics-Guided Geometric Diffusion for Macro Placement Generation
POSTECH Institute of Artificial Intelligence（POSTECH人工智能研究所）；KAIST InnoCORE LLM（韩国科学技术院InnoCORE语言模型实验室）；Seoul National University（首尔国立大学）；Pohang University of Science and Technology（釜山科学技术大学）
