PPAPlace：用于芯片布局优化的可微跨阶段目标
PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization
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- University of Alberta（阿尔伯塔大学）
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中文总结 AI 辅助
PPAPlace是一种时序驱动的可微代理模型，以全局布线后标签训练，通过双流预测器结合图注意力与空间卷积，在ChiPBench测试电路上较分层基准显著提升WNS与TNS并保持功耗和可布线性。
中文摘要 AI 辅助
宏布局显著影响芯片布线后性能、功耗与面积（PPA）。大多数布局方法以半周长线长（HPWL）为主要优化目标，但近期基准测试显示，HPWL与布线后时序指标（如最坏负 Slack（WNS）和总负 Slack（TNS））的相关性接近零，导致所有6种受评估的人工智能（AI）布局器的PPA均劣于分层基准。近期研究尝试训练跨阶段预测器以缩小该差距，但现有方法仅关注宏单元表示，且以布线前指标为训练标签。对10个电路在4个设计流程阶段的标签保真度研究表明，HPWL与布线前时序无法准确反映最终布线后时序排名，而全局布线后阶段在最终时序保真度与标签生成成本效益间实现了最佳平衡。基于该发现，PPAPlace是一种时序驱动的可微代理模型，可从宏单元与标准单元布局预测布线后PPA。该代理模型为双流预测器，结合芯片网表上的图注意力机制与布局网格上的空间卷积，以全局布线后标签训练，预测的WNS与TNS梯度可端到端反向传播至单元坐标。PPAPlace以两种方式利用这些梯度：作为协同目标注入分析布局器的优化循环（PPAPlace-CoOpt），以及作为布局后优化步骤通过投影梯度下降调整宏单元位置（PPAPlace-Refine）。在5个未参与训练的ChiPBench测试电路上，PPAPlace使用同一预测器且未对测试电路进行重新训练，较分层基准将平均WNS与TNS分别提升22%与51%，同时保持功耗与可布线性。代码可在this https URL获取。
英文摘要
Macro placement significantly affects a chip's post-route performance, power, and area (PPA). Most placement methods optimize half-perimeter wirelength (HPWL) as the primary objective. However, recent benchmarking shows a near-zero correlation between HPWL and post-route timing metrics such as the worst negative slack (WNS) and total negative slack (TNS). As a result, all six evaluated artificial intelligence (AI) placers degraded PPA relative to the hierarchical baseline. Recent efforts have tried to train cross-stage predictors to close this gap. However, existing methods focus on macro-only representations and use pre-route metrics as training labels. A label fidelity study of ten circuits at four design flow stages reveals that HPWL and pre-route timing poorly reflect final post-route timing rankings. In contrast, post-global-routing achieves the best balance between final timing fidelity and label generation cost-effectiveness. Based on this finding, PPAPlace is a timing-driven differentiable surrogate predicting post-route PPA from macro and standard-cell placements. The surrogate is a dual-stream predictor that combines graph attention over the chip netlist with spatial convolution over the placement grid. It is trained on post-global-routing labels. The predicted WNS and TNS gradients flow end-to-end back to cell coordinates. PPAPlace exploits these gradients in two ways: as a co-objective injected into an analytical placer's optimization loop (PPAPlace-CoOpt), and as a post-placement refinement step that adjusts macro positions via projected gradient descent (PPAPlace-Refine). On five ChiPBench test circuits excluded from training, PPAPlace improves average WNS and TNS by 22\% and 51\% over the hierarchical baseline while preserving power and routability, using the same predictor without test-circuit retraining. Code is available at https://github.com/ValleyC/PPAPlace.
