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arXiv 2311.03379cs.ARcs.PL
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HIDA:一种面向高层次综合的分层数据流编译器

HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis

Hanchen Ye, Hyegang Jun, Deming Chen

AI总结:

针对现有HLS工具依赖人工探索数据流设计空间导致设计次优的问题,提出分层HLS框架HIDA,通过分层数据流表示与自动分层优化,在FPGA上实现了优于现有HLS工具和RTL神经网络加速器的吞吐量。

摘要:

数据流架构因有望缓解冯·诺依曼架构固有的内存墙带来的挑战而日益流行。与此同时,高层次综合(HLS)已被证明是一种能在短开发周期内生成高效数据流架构的有效设计方法。然而,现有HLS工具依赖开发者探索庞大的数据流设计空间,最终导致设计并非最优。随着HLS设计规模的增长,这一问题尤为突出。为解决这些挑战,我们提出了HIDA,这是一种新型可扩展的分层HLS框架,能够系统地将算法描述转换为硬件上的数据流实现。我们首先提出了一组高效通用的数据流表示方法,用于对分层数据流结构进行建模。基于这些表示方法,我们开发了一个自动化优化器,它根据数据流固有的分层结构,将数据流优化问题分解为多个层级。我们以FPGA为评估平台,对一组用PyTorch建模的神经网络进行测试,结果显示,与最先进(SOTA)的HLS优化工具相比,HIDA的吞吐量最高提升了8.54倍。此外,尽管HIDA完全自动化且能够处理各类应用,但其在FPGA上的吞吐量比基于RTL的最先进神经网络加速器高出1.29倍。

英文摘要:

Dataflow architectures are growing in popularity due to their potential to mitigate the challenges posed by the memory wall inherent to the Von Neumann architecture. At the same time, high-level synthesis (HLS) has demonstrated its efficacy as a design methodology for generating efficient dataflow architectures within a short development cycle. However, existing HLS tools rely on developers to explore the vast dataflow design space, ultimately leading to suboptimal designs. This phenomenon is especially concerning as the size of the HLS design grows. To tackle these challenges, we introduce HIDA, a new scalable and hierarchical HLS framework that can systematically convert an algorithmic description into a dataflow implementation on hardware. We first propose a collection of efficient and versatile dataflow representations for modeling the hierarchical dataflow structure. Capitalizing on these representations, we develop an automated optimizer that decomposes the dataflow optimization problem into multiple levels based on the inherent dataflow hierarchy. Using FPGAs as an evaluation platform, working with a set of neural networks modeled in PyTorch, HIDA achieves up to 8.54$\times$ higher throughput compared to the state-of-the-art (SOTA) HLS optimization tool. Furthermore, despite being fully automated and able to handle various applications, HIDA achieves 1.29$\times$ higher throughput over the SOTA RTL-based neural network accelerators on an FPGA.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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