DFIT：面向异构数据流加速器的检测工具构建框架
DFIT: A Framework for Building Instrumentation Tools Across Heterogeneous Dataflow Accelerators
AI总结：
DFIT是专为数据流架构设计的检测框架，可在不修改工具逻辑的情况下实现异构数据流加速器的跨平台检测，在Cerebras等三类硬件上开销为3.53%-13.62%，为AI加速器性能分析工具奠定基础。
摘要：
新兴数据流加速器为机器学习工作负载提供了卓越的能效和吞吐量，但开发者在进行性能分析时仍难以获取其内部信息。与具备支持细粒度内省的检测框架的CPU和GPU不同，数据流硬件几乎不暴露任何信息。这种透明度的缺失限制了编译器工程师、系统设计师和应用开发者分析、调优或调试加速器行为的能力。本文中，我们提出DFIT（DataFlow Accelerator Instrumentation Tool，数据流加速器检测工具），这是一个专为数据流架构设计的检测框架。DFIT在图IR和后端降级阶段，利用语义程序表示直接检测操作、区域和编译器变换，捕获反映真实计算数据流的高级语义相关数据，这些数据可导出用于可视化和分析。我们的方法展示了如何将检测从传统硬件推广到支持异构架构，在不修改工具逻辑的情况下提供可移植性。通过打开数据流执行的黑箱，DFIT为AI加速器的新型性能分析工具奠定了基础，为跨异构系统实现可复现、架构感知的内省提供了可行路径，弥合了编译器设计、运行时调度与硬件实现之间长期存在的可见性差距。在Cerebras、SambaNova和TPU上的评估显示，不同检测模式下的实际开销为3.53%-13.62%，具备稳健的跨平台可移植性。
英文摘要：
Emerging dataflow accelerators offer exceptional energy efficiency and throughput for machine learning workloads, yet remain largely opaque to developers for performance analysis. Unlike CPUs and GPUs, where instrumentation frameworks enable fine-grained introspection, dataflow hardware exposes little information. This lack of transparency limits the ability of compiler engineers, system designers, and application developers to analyze, tune, or debug accelerator behavior. In this paper, we introduce DFIT (DataFlow Accelerator Instrumentation Tool), an instrumentation framework designed specifically for dataflow architectures. DFIT directly instruments operations, regions, and compiler transformations at the graph IR and backend-lowering stages using semantic program representation. DFIT captures high-level, semantically meaningful data that reflect the true dataflow of computation. These data can be exported for visualization and analysis. Our approach demonstrates how instrumentation can be generalized beyond traditional hardware to support heterogeneous architectures, providing portability without modifying tool logic. By opening the black box of dataflow execution, DFIT establishes a foundation for new classes of performance analysis tools for AI accelerators. It provides a practical path toward reproducible, architecture-aware introspection across heterogeneous systems, bridging the long-standing visibility gap between compiler design, runtime scheduling, and hardware realization. Evaluation across Cerebras, SambaNova, and TPU shows practical overhead of 3.53%-13.62% across instrumentation modes with robust cross-platform portability.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
