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arXiv 2310.02474physics.ins-dethep-ex
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智能像素传感器:借助深度学习实现像素簇的片上滤波

Smart pixel sensors: towards on-sensor filtering of pixel clusters with deep learning

Jieun Yoo, Jennet Dickinson, Morris Swartz, Giuseppe Di Guglielmo, Alice Bean, Douglas Berry, Manuel Blanco Valentin, Karri DiPetrillo, Farah Fahim, Lindsey Gra… 展开作者

Jieun Yoo, Jennet Dickinson, Morris Swartz, Giuseppe Di Guglielmo, Alice Bean, Douglas Berry, Manuel Blanco Valentin, Karri DiPetrillo, Farah Fahim, Lindsey Gray, James Hirschauer, Shruti R. Kulkarni, Ron Lipton, Petar Maksimovic, Corrinne Mills, Mark S. Neubauer, Benjamin Parpillon, Gauri Pradhan, Chinar Syal, Nhan Tran, Dahai Wen, Aaron Young

AI总结:

针对下一代高粒度像素探测器的超高数据速率问题,提出可嵌入片上读出系统的神经网络,通过滤除低动量径迹击中实现54.4%-75.4%的数据量缩减,且芯片功耗与面积均满足集成要求。

摘要:

高粒度像素探测器使得带电粒子径迹的测量精度不断提升。下一代探测器要求进一步缩小像素尺寸,这将带来前所未有的数据速率,超过高亮度大型强子对撞机(High Luminosity Large Hadron Collider)的预期水平。能够处理约40MHz速率的输入数据、并在探测器像素区域内实时智能降维的信号处理技术,将提升高亮度条件下的物理研究性能,还能支撑目前无法开展的物理分析工作。利用沉积在小像素阵列中的电荷簇形状,可通过本地定制的神经网络提取穿过探测器的粒子的物理性质。在本次首次验证研究中,我们提出了一种可嵌入传感器片上读出系统的神经网络,它能滤除低动量径迹的击中信号,将探测器的数据量降低54.4%至75.4%。该网络采用28纳米CMOS工艺作为定制读出集成电路进行设计与仿真,预计工作功耗低于300微瓦,面积小于0.2平方毫米。本文还研究了电荷簇的时间演化特性,以展示未来可能的性能提升方向,同时讨论了未来可提升效率、数据压缩效果和单位面积功耗的算法与技术改进方向。

英文摘要:

Highly granular pixel detectors allow for increasingly precise measurements of charged particle tracks. Next-generation detectors require that pixel sizes will be further reduced, leading to unprecedented data rates exceeding those foreseen at the High Luminosity Large Hadron Collider. Signal processing that handles data incoming at a rate of O(40MHz) and intelligently reduces the data within the pixelated region of the detector at rate will enhance physics performance at high luminosity and enable physics analyses that are not currently possible. Using the shape of charge clusters deposited in an array of small pixels, the physical properties of the traversing particle can be extracted with locally customized neural networks. In this first demonstration, we present a neural network that can be embedded into the on-sensor readout and filter out hits from low momentum tracks, reducing the detector's data volume by 54.4-75.4%. The network is designed and simulated as a custom readout integrated circuit with 28 nm CMOS technology and is expected to operate at less than 300 $μW$ with an area of less than 0.2 mm$^2$. The temporal development of charge clusters is investigated to demonstrate possible future performance gains, and there is also a discussion of future algorithmic and technological improvements that could enhance efficiency, data reduction, and power per area.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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