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arXiv 2306.04089cs.LOcs.SYeess.SYmath.DS
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通过可达性分析对线性时不变系统进行信号时序逻辑规范的全自动验证

Fully Automated Verification of Linear Time-Invariant Systems against Signal Temporal Logic Specifications via Reachability Analysis

Niklas Kochdumper, Stanley Bak

AI总结:

本文提出一种面向线性系统的全自动验证器,通过自动细化可达性分析参数并结合可达集时序逻辑与依赖保持,实现对信号时序逻辑规范的自动证明或证伪。

摘要:

虽然可达性分析是动态系统形式化验证中最有前景的方法之一,但阻碍其更广泛应用的一个主要缺点是需要手动调整算法参数,例如时间步长。如果目标是验证系统是否满足由信号时序逻辑公式描述的复杂规范,手动调整尤其成问题,因为可达集的紧致性对规范满足情况的影响对于人类来说通常难以直观判断。我们通过一个面向线性系统的全自动验证器来解决这一问题,该验证器会自动细化可达性分析的所有参数,直到能够证明或证伪该系统对于所有初始状态和所有不确定输入都满足某个信号时序逻辑公式。我们的验证器将可达集时序逻辑与依赖保持相结合,获得一种模型检测方法,其过近似误差在参数充分调整时收敛到零。虽然为简单起见,本文重点研究线性系统,但我们提出的总体概念同样可以应用于非线性和混合系统。

英文摘要:

While reachability analysis is one of the most promising approaches for formal verification of dynamic systems, a major disadvantage preventing a more widespread application is the requirement to manually tune algorithm parameters such as the time step size. Manual tuning is especially problematic if one aims to verify that the system satisfies complicated specifications described by signal temporal logic formulas since the effect the tightness of the reachable set has on the satisfaction of the specification is often non-trivial to see for humans. We address this problem with a fully-automated verifier for linear systems, which automatically refines all parameters for reachability analysis until it can either prove or disprove that the system satisfies a signal temporal logic formula for all initial states and all uncertain inputs. Our verifier combines reachset temporal logic with dependency preservation to obtain a model checking approach whose over-approximation error converges to zero for adequately tuned parameters. While we in this work focus on linear systems for simplicity, the general concept we present can equivalently be applied for nonlinear and hybrid systems.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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