通过严格理解DRAM的内在操作来提高DRAM的性能、可靠性和安全性
Improving DRAM Performance, Reliability, and Security by Rigorously Understanding Intrinsic DRAM Operation
摘要：
DRAM是现代系统中用于主存储器的主要技术。不幸的是，随着DRAM规模缩小到更小的技术节点，它在数据完整性和延迟方面都面临着关键挑战，这严重影响了整体系统的可靠性，安全性和性能。为了为未来的系统开发可靠、安全和高性能的基于DRAM的主存储器，严格地表征、分析和理解各个方面（例如，可靠性、保持性、等待时间、RowHammer漏洞）以及它们的架构。本论文的目标是1）开发技术和基础设施，使这种严格的表征，分析和理解，和2）使新的机制，以提高DRAM的性能，可靠性和安全性的基础上开发的理解。为此，在本论文中，我们1）设计、实现并原型化了一种新的实用且灵活的基于FPGA的DRAM表征基础设施（称为SoftMC），2）使用DRAM表征基础设施开发新的实验方法（称为U-TRR），以揭示现有专有的操作-DRAM RowHammer保护机制并设计新的RowHammer访问模式以有效地规避这些RowHammer保护机制，3）提出一种新的DRAM架构，称为SelfManaging DRAM，用于实现自主和有效的DRAM内维护操作，其不仅实现更好的性能、效率和可靠性，而且还实现对DRAM芯片的更快和更容易的改变的采用，以及4）提出了一种通用DRAM衬底，称为复制行（CROW）衬底，其实现用于改进DRAM性能、能量消耗和可靠性的新机制。
英文摘要：
DRAM is the primary technology used for main memory in modern systems. Unfortunately, as DRAM scales down to smaller technology nodes, it faces key challenges in both data integrity and latency, which strongly affect overall system reliability, security, and performance. To develop reliable, secure, and high-performance DRAM-based main memory for future systems, it is critical to rigorously characterize, analyze, and understand various aspects (e.g., reliability, retention, latency, RowHammer vulnerability) of existing DRAM chips and their architecture. The goal of this dissertation is to 1) develop techniques and infrastructures to enable such rigorous characterization, analysis, and understanding, and 2) enable new mechanisms to improve DRAM performance, reliability, and security based on the developed understanding. To this end, in this dissertation, we 1) design, implement, and prototype a new practical-to-use and flexible FPGA-based DRAM characterization infrastructure (called SoftMC), 2) use the DRAM characterization infrastructure to develop a new experimental methodology (called U-TRR) to uncover the operation of existing proprietary in-DRAM RowHammer protection mechanisms and craft new RowHammer access patterns to efficiently circumvent these RowHammer protection mechanisms, 3) propose a new DRAM architecture, called SelfManaging DRAM, for enabling autonomous and efficient in-DRAM maintenance operations that enable not only better performance, efficiency, and reliability but also faster and easier adoption of changes to DRAM chips, and 4) propose a versatile DRAM substrate, called the Copy-Row (CROW) substrate, that enables new mechanisms for improving DRAM performance, energy consumption, and reliability.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
