RevaMp3D：为具有单体集成逻辑和内存的系统设计处理器核心和缓存层次结构
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory
AI总结：
RevaMp3D通过移除共享缓存、优化流水结构、利用M3D内存等方法，提升处理器性能并降低能耗。
摘要：
最近的纳米技术进步使多层内存和逻辑层的单体3D（M3D）集成成为可能，允许在单个芯片上进行细粒度连接，并显著缓解主内存瓶颈。我们展示，在一种先进的基于M3D的系统上，对于各种工作负载，性能和能耗瓶颈从主内存转移到了处理器核心和缓存层次结构。因此，有必要重新审视当前设计，这些设计传统上都是为解决内存瓶颈而定制的。基于我们的设计空间探索的洞察，我们提出了RevaMp3D，引入了五个关键变化。首先，我们提出移除共享的最后级别缓存，因为这在所有工作负载中都能提供与增加其大小或减少其延迟相当或更高的加速效果。其次，由于提高L1缓存延迟对性能影响很大，我们通过利用M3D布局来缩短其导线。第三，我们将移除缓存所释放的面积用于扩大和扩展流水结构，以容纳更多在飞行的请求，这些请求可以高效地由M3D内存服务。为了避免这些较大结构带来的延迟惩罚，我们利用M3D布局。第四，为了促进高线程级并行性，我们提出了一种新的细粒度同步技术，利用M3D的密集层间连接性。第五，我们利用M3D主内存来缓解核心瓶颈。我们提出了一种处理器前端设计，该设计会记住重复获取、解码和重排序的指令，将它们存储在主内存中，并在可能时关闭相关核心部分。RevaMp3D相比最先进的M3D系统提供了1.2倍至2.9倍的速度提升和1.2倍至1.4倍的能耗降低。我们还分析了RevaMp3D的设计决策在各种内存延迟下的表现，以促进延迟感知的设计决策。
英文摘要：
Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip, allowing for fine-grained connections between layers and significantly alleviating main memory bottlenecks. We show for a variety of workloads, on a state-of-the-art M3D-based system, that the performance and energy bottlenecks shift from main memory to the processor core and cache hierarchy. Therefore, there is a need to revisit current designs that have been conventionally tailored to tackle the memory bottleneck. Based on the insights from our design space exploration, we propose RevaMp3D, introducing five key changes. First, we propose removing the shared last-level cache, as this delivers speedups comparable to or exceeding those from increasing its size or reducing its latency across all workloads. Second, since improving L1 cache latency has a large impact on performance, we reduce L1 latency by leveraging an M3D layout to shorten its wires. Third, we repurpose the area from the removed cache to widen and scale up pipeline structures, accommodating more in-flight requests that are efficiently served by M3D memory. To avoid latency penalties from these larger structures, we leverage M3D layouts. Fourth, to facilitate high thread-level parallelism, we propose a new fine-grained synchronization technique, using M3D's dense inter-layer connectivity. Fifth, we leverage the M3D main memory to mitigate the core bottlenecks. We propose a processor frontend design that memoizes the repetitive fetched, decoded, and reordered instructions, stores them in main memory, and turns off the relevant parts of the core when possible. RevaMp3D provides 1.2x-2.9x speedup and 1.2x-1.4x energy reduction compared to a state-of-the-art M3D system. We also analyze RevaMp3D's design decisions across various memory latencies to facilitate latency-aware design decisions.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
