CMOS电路中TSV互连线感应耦合的研究
Overview and study of the 3D-TSV interconnects induced coupling in CMOS circuits
摘要：
半导体工业的快速发展将传统的二维技术在缩放、性能和成本因素方面推向了极限。这些挑战推动了3D技术在各种集成电路生产中的应用。3D集成的众多特征之一是使用硅通孔（TSV）将多层组装成单个堆叠。这种工艺最初是为存储芯片开发的，后来被用于微电子其他领域的许多应用。本研究的目的是评估3D-TSV互连对MOS晶体管和CMOS电路性能的影响。这是通过使用能够描述TSV在电路级引起的衬底耦合的数值和分析模型来实现的。提出的分析方法，使研究和优化的性能，不仅MOS器件，而且大型CMOS电路与3D互连作为各种技术和电气参数的函数。
英文摘要：
The semiconductor industry's rapid advancement pushes conventional two-dimensional technology to its utmost limitations in terms of scaling, performance, and cost factors. These challenges drive the usage of 3D technology in the production of various Integrated Circuits. One of the numerous features of 3D Integration is the use of Through Silicon Vias (TSVs) for the assembly of multilayers into a single stack. This process, which was initially developed for memory chips, has been used afterward in many applications in other areas of microelectronics. The purpose of this research is to assess the effect of 3D-TSV interconnection on the performance of MOS transistors and CMOS circuits. This is accomplished using numerical and analytical models capable of describing the substrate coupling induced by TSV at the circuit level. The analytical approach proposed enables the study and optimization of the performance, not only of MOS devices but also large CMOS circuits with 3D interconnects as a function of various technological and electrical parameters.
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