Leena Diehl, Marta Baselga, Ingrid Maria Gregor, Marc Hauser, Tomasz Hemperek, Jan Cedric Hönig, Karl Jakobs, Sven Mägdefessel, Ulrich Parzefall, Arturo Rodrigu… 展开作者
Leena Diehl, Marta Baselga, Ingrid Maria Gregor, Marc Hauser, Tomasz Hemperek, Jan Cedric Hönig, Karl Jakobs, Sven Mägdefessel, Ulrich Parzefall, Arturo Rodriguez, Surabhi Sharma, Dennis Sperlich, Liv Wiik-Fuchs, Tianyang Wang
Recent advances in CMOS imaging sensor technology , e.g. in CMOS pixel sensors, have proven that the CMOS process is radiation tolerant enough to cope with certain radiation levels required for tracking layers in hadron collider experiments. With the ever-increasing area covered by silicon tracking detectors cost effective alternatives to the current silicon sensors and more integrated designs are desirable. This article describes results obtained from laboratory measurements of silicon strip sensors produced in a passive p-CMOS process. Electrical characterization and charge collection measurements with a 90Sr source and a laser with infrared wavelength showed no effect of the stitching process on the performance of the sensor.
Characterization of Passive CMOS Strip Detectors After Proton Irradiation
TU Dortmund（多特蒙德工业大学）；Deutsches Elektronen Synchrotron DESY（德国电子同步加速器中心）；University of Bonn（波恩大学）；Albert-Ludwigs-Universität Freiburg（弗赖堡大学）；Fachhochschule Dortmund（多特蒙德应用技术大学）
Both the current upgrades to accelerator-based HEP detectors (e.g. ATLAS, CMS) and also future projects (e.g. CEPC, FCC) feature large-area silicon-based tracking detectors. We are investigating the feasibility of using CMOS foundries to fabricate silicon radiation detectors, both for pixels and for large-area strip sensors. A successful proof of concept would open the market potential of CMOS foundries to the HEP community, which would be most beneficial in terms of availability, throughput and cost. In addition, the availability of multi-layer routing of signals will provide the freedom to o…
The radiation hardness of passive CMOS pixel sensors fabricated in 150 nm LFoundry technology is investigated. CMOS process lines are especially of interest for large-scale silicon detectors as they offer high production throughput at comparatively low cost. Moreover, several features like poly-silicon resistors, MIM-capacitors and several metal layers are available which can help enhance the sensor design. The performance of a 100 $\mathrmμ$m thin passive CMOS sensor with a pixel pitch of 50 $\mathrmμ$m at different irradiation levels, 5 $\times$ 10$^{15}$n$_{\mathrm{eq}}$cm$^{-2}$ and 1 $\ti…
We are investigating the feasibility of using CMOS foundries to fabricate silicon detectors, both for pixels and for large-area strip sensors. The availability of multi-layer routing will provide the freedom to optimize the sensor geometry and the performance, with biasing structures in poly-silicon layers and MIM-capacitors allowing for AC coupling. A prototyping production of strip test-structures and RD53A compatible pixel sensors was recently completed at LFoundry in a 150$\,$nm CMOS process. This paper will focus on the characterization of irradiated and non-irradiated pixel modules, comp…
High Energy Particle Physics experiments at the LHC use hybrid silicon detectors, in both pixel and strip geometry, for their inner trackers. These detectors have proven to be very reliable and performant. Nevertheless, there is great interest in the development of depleted CMOS silicon detectors, which could achieve similar performances at lower cost of production and complexity. We present recent developments of this technology in the framework of the ATLAS CMOS demonstrator project. In particular, studies of two active sensors from LFoundry, CCPD_LF and LFCPIX, and the first fully monolithi…
The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a deplet…
The planned HL-LHC (High Luminosity LHC) in 2025 is being designed to maximise the physics potential through a sizable increase in the luminosity up to 6*10^34 cm^-2 s^-1. A consequence of this increased luminosity is the expected radiation damage at 3000 fb^-1 after ten years of operation, requiring the tracking detectors to withstand fluences to over 1*10^16 1 MeV n_eq/cm^2 . In order to cope with the consequent increased readout rates, a complete re-design of the current ATLAS Inner Detector (ID) is being developed as the Inner Tracker (ITk). Two proposed detectors for the ATLAS strip track…
The upgrade to the High Luminosity Large Hadron Collider will pose unprecedented challenges to the tracking systems of all experiments. Recent advancement of active pixel detectors designed in CMOS processes provide attractive alternatives to the well-established hybrid design using passive sensors. This article presents studies with a high-voltage CMOS active pixel sensor designed for the ATLAS tracker upgrade. The sensor is glued to the read-out chip of the Insertable B-Layer. The device under test is structured in smaller pixels than those of the attached read-out chip with information on t…
In this paper results of Edge-TCT and I-V measurements with passive test structures made in LFoundry 150 nm HV-CMOS process on p-type substrates with different initial resistivities ranging from 0.5 to 3 k$Ω$cm are presented. Samples were irradiated with reactor neutrons up to a fluence of 2$\cdot$10$^{15}$ n$_{\mathrm{eq}}$/cm$^2$. Depletion depth was measured with Edge-TCT. Effective space charge concentration $N_{\mathrm{eff}}$ was estimated from the dependence of depletion depth on bias voltage and studied as a function of neutron fluence. Dependence of $N_{\mathrm{eff}}$ on fluence change…
We report on the development of a front-end ASIC for silicon-strip detectors of the J-PARC Muon g-2/EDM experiment. This experiment aims to measure the muon anomalous magnetic moment and electric dipole moment precisely to explore new physics beyond the Standard Model. Since the time and momentum of positrons from muon decay are key information in the experiment, a fast response with high granularity is demanded to silicon-strip detectors as the positron tracker. The readout ASIC is thus required to tolerate a high hit rate of 1.4 MHz per strip and to have deep memory for the period of 40 us w…
A new silicon-strip readout chip named "SliT" has been developed for the measurement of the muon anomalous magnetic moment and electric dipole moment at J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with mixed-signal integrated circuits. An analog circuit incorporates a conventional charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators for each of 128 identical channels. A digital part includes storage memories, an event building block, a serializer, and LVDS drivers. A distinct feature of the SliT is utilization of the zero-cross architecture, w…
The Two Photon Absorption - Transient Current Technique (TPA-TCT) was used to investigate a silicon strip detector with illumination from the top. Measurement and analysis techniques for the TPA-TCT of segmented devices are presented and discussed using a passive strip CMOS detector as an example. The influence of laser beam clipping and reflection is shown and a method that allows to compensate these intensity related effects for the investigation of the electric field is introduced and successfully employed. Besides, the mirror technique is introduced, which exploits reflection at a metallis…
Investigation of HV-CMOS sensors for use as a tracking detector in the ATLAS experiment at the upgraded LHC (HL-LHC) has recently been an active field of research. A potential candidate for a pixel detector built in Silicon-On-Insulator (SOI) technology has already been characterized in terms of radiation hardness to TID (Total Ionizing Dose) and charge collection after a moderate neutron irradiation. In this article we present results of an extensive irradiation hardness study with neutrons up to a fluence of 1x10e16 neq/cm2. Charge collection in a passive pixelated structure was measured by …
Development of a Silicon-Based Ultra-Fast X-Ray Beam Size Monitor for SuperKEKB
University of Hawaii（夏威夷大学）；High Energy Accelerator Research Organization (KEK)（高能加速器研究机构）；Department of Physics, University of Tokyo（东京大学物理系）；The Graduate University for Advanced Studies (SOKENDAI)（综合研究大学院大学）；SLAC National Accelerator Laboratory（SLAC国家加速器实验室）；Graduate School of Science, Nagoya University（名古屋大学理学研究科）
