带符号位片架构的高能效密集DNN加速
Energy-efficient Dense DNN Acceleration with Signed Bit-slice Architecture
摘要：
随着要在移动片上系统（SoC）上执行的深度神经网络（DNN）的数量增加，移动SoC在其有限的硬件资源和功率预算内遭受实时DNN加速。虽然以前的移动神经处理单元（NPU）利用了低比特计算和稀疏性，但它无法加速高精度和密集的DNN。本文提出了一种节能的有符号位片架构，该架构通过利用有符号位片的大量零值来加速高精度和密集的DNN。所提出的带符号位片表示（SBR）通过从其较低阶位片借用$1$值来将带符号$1111_{2}$位片改变为$0000_{2}$。因此，即使在密集的DNN中，它也会生成大量的零位片。此外，它平衡2的补码数据的正值和负值，允许基于位片的输出推测，其预先计算位片的高阶并且跳过位片的剩余密集低阶。有符号位片架构压缩并跳过零输入有符号位片，零跳过单元还通过将推测的输入掩蔽为零来支持输出跳过。此外，异构片上网络有利于开发数据重用性和减少传输带宽。本文介绍了一种专用的指令集结构（ISA）和一种用于控制带符号位片结构的分级指令译码器。最后，有符号位片架构在$\times3.65$更高的面积效率、$\times3.88$更高的能量效率和$\times5.35$更高的吞吐量上优于先前的位片加速器位融合。
英文摘要：
As the number of deep neural networks (DNNs) to be executed on a mobile system-on-chip (SoC) increases, the mobile SoC suffers from the real-time DNN acceleration within its limited hardware resources and power budget. Although the previous mobile neural processing units (NPUs) take advantage of low-bit computing and exploitation of the sparsity, it is incapable of accelerating high-precision and dense DNNs. This paper proposes energy-efficient signed bit-slice architecture which accelerates both high-precision and dense DNNs by exploiting a large number of zero values of signed bit-slices. Proposed signed bit-slice representation (SBR) changes signed $1111_{2}$ bit-slice to $0000_{2}$ by borrowing a $1$ value from its lower order of bit-slice. As a result, it generates a large number of zero bit-slices even in dense DNNs. Moreover, it balances the positive and negative values of 2's complement data, allowing bit-slice based output speculation which pre-computes high order of bit-slices and skips the remaining dense low order of bit-slices. The signed bit-slice architecture compresses and skips the zero input signed bit-slices, and the zero skipping unit also supports the output skipping by masking the speculated inputs as zero. Additionally, the heterogeneous network-on-chip (NoC) benefits the exploitation of data reusability and reduction of transmission bandwidth. The paper introduces a specialized instruction set architecture (ISA) and a hierarchical instruction decoder for the control of the signed bit-slice architecture. Finally, the signed bit-slice architecture outperforms the previous bit-slice accelerator, Bit-fusion, over $\times3.65$ higher area-efficiency, $\times3.88$ higher energy-efficiency, and $\times5.35$ higher throughput.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
