arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2408.13617cs.AR
收藏

SiTe CiM:面向超低精度深度神经网络的带符号三值存内计算

SiTe CiM: Signed Ternary Computing-in-Memory for Ultra-Low Precision Deep Neural Networks

Niharika Thakuria, Akul Malhotra, Sandeep K. Thirumala, Reena Elangovan, Anand Raghunathan, Sumeet K. Gupta

AI总结:

提出支持带符号三值输入与权重点积的存内计算架构SiTe-CiM,基于交叉耦合位单元设计两种变体,在多种存储技术上实现显著降低延迟与能耗,并大幅提升系统吞吐量。

摘要:

三值深度神经网络(DNN)凭借其超低精度带来的低功耗运行优势,且仅有轻微的精度下降,在高度受限能耗系统中展现出巨大潜力。为在此类系统中实现高能效的硬件基础,我们提出了一种具备计算能力的存储器设计,称为SiTe-CiM,其特色在于支持带符号三值(SiTe)输入与权重之间点积的存内计算(CiM)。SiTe CiM基于两个位单元的交叉耦合,以实现带符号三值域中的点积CiM。我们基于8T-SRAM、3T嵌入式DRAM(3T-eDRAM)和3T铁电金属FET(FEMFET)存储器探索了SiTe CiM。我们提出了该技术的两种变体,即SiTe CiM I/II。在SiTe CiM I中,每个单元采用两个额外晶体管进行交叉耦合,实现了快速CiM操作,但会带来18%至34%的面积开销(与标准三值存储器相比)。在SiTe CiM II中,一列中每16个单元利用四个额外晶体管,因此仅产生6%的面积成本(但CiM速度比SiTe CiM I慢)。基于阵列分析,与各自的近存计算对应方案相比,在所考量的各种技术中,我们的设计实现了高达88%的CiM延迟降低和78%的CiM节能。此外,我们通过将SiTe CiM I/II阵列整合到三值DNN加速器中进行系统级分析,结果表明,与近存计算三值DNN加速器相比,吞吐量提升高达7倍,能耗降低高达2.5倍。

英文摘要:

Ternary Deep Neural Networks (DNN) have shown a large potential for highly energy-constrained systems by virtue of their low power operation (due to ultra-low precision) with only a mild degradation in accuracy. To enable an energy-efficient hardware substrate for such systems, we propose a compute-enabled memory design, referred to as SiTe-CiM, which features computing-in-memory (CiM) of dot products between signed ternary (SiTe) inputs and weights. SiTe CiM is based on cross-coupling of two bit cells to enable CiM of dot products in the signed ternary regime. We explore SiTe CiM with 8T-SRAM, 3T-embedded DRAM (3T-eDRAM) and 3T-ferroelectric metal FET (FEMFET) memories. We propose two flavors of this technique, namely SiTe CiM I/II. In SiTe CiM I, we employ two additional transistors per cell for cross-coupling, achieving fast CiM operations, albeit incurring an area overhead ranging from 18% to 34% (compared to standard ternary memories). In SiTe CiM II, four extra transistors are utilized for every 16 cells in a column, thereby incurring only 6% area cost (but leading to slower CiM than SiTe CiM I). Based on the array analysis, our designs achieve up to 88% lower CiM latency and 78% CiM energy savings across various technologies considered, as compared to their respective near-memory computing counterparts. Further, we perform system level analysis by incorporating SiTe CiM I/II arrays in a ternary DNN accelerator and show up to 7X throughput boost and up to 2.5X energy reduction compared to the near-memory ternary DNN accelerators.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

↑