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arXiv 2201.07634cs.ARcs.AI
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FAT:一个三值权值神经网络的内存加速器

FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

Nanyang Technological University(南洋理工大学)

Shien Zhu, Luan H. K. Duong, Hui Chen, Di Liu, Weichen Liu

摘要:

卷积神经网络(CNN)在各种应用中表现出优异的性能,但具有高计算复杂性。应用量化来减少CNN的延迟和存储成本。在量化方法中,二进制和三进制权重网络(BWN和TWN)相对于8位和4位量化具有独特的优势。它们用加法取代CNN中的乘法运算,这在内存计算(IMC)设备上很受欢迎。BWN的IMC加速已经被广泛研究。然而,尽管小波网络比小波网络具有更高的精度和更好的稀疏性,但针对小波网络的内模传播加速研究有限。现有IMC设备上的TW是低效的,因为稀疏性没有被很好地利用,并且加法操作是低效的。在本文中,我们提出FAT作为一种新的IMC加速器的TWN。首先,我们提出了一个稀疏加法控制单元,它利用TWNs的稀疏性跳过零权重的空操作。其次,我们提出一种基于记忆体感测放大器的快速加法方案,以避免进位传播和将进位写回存储单元的时间开销。第三,我们进一步提出了一种组合静态数据映射,以减少激活和权重的数据移动,并增加跨内存列的并行性。仿真结果表明,加法运算在感测放大器的水平,FAT实现了2.00倍的加速比,1.22倍的功率效率,和1.22倍的面积效率相比,国家的最先进的IMC加速器ParaPIM。在平均稀疏度为80%的网络上,FAT与ParaPIM相比实现了10.02倍的加速比和12.19倍的能效。

英文摘要:

Convolutional Neural Networks (CNNs) demonstrate excellent performance in various applications but have high computational complexity. Quantization is applied to reduce the latency and storage cost of CNNs. Among the quantization methods, Binary and Ternary Weight Networks (BWNs and TWNs) have a unique advantage over 8-bit and 4-bit quantization. They replace the multiplication operations in CNNs with additions, which are favoured on In-Memory-Computing (IMC) devices. IMC acceleration for BWNs has been widely studied. However, though TWNs have higher accuracy and better sparsity than BWNs, IMC acceleration for TWNs has limited research. TWNs on existing IMC devices are inefficient because the sparsity is not well utilized, and the addition operation is not efficient. In this paper, we propose FAT as a novel IMC accelerator for TWNs. First, we propose a Sparse Addition Control Unit, which utilizes the sparsity of TWNs to skip the null operations on zero weights. Second, we propose a fast addition scheme based on the memory Sense Amplifier to avoid the time overhead of both carry propagation and writing back the carry to memory cells. Third, we further propose a Combined-Stationary data mapping to reduce the data movement of activations and weights and increase the parallelism across memory columns. Simulation results show that for addition operations at the Sense Amplifier level, FAT achieves 2.00X speedup, 1.22X power efficiency, and 1.22X area efficiency compared with a State-Of-The-Art IMC accelerator ParaPIM. FAT achieves 10.02X speedup and 12.19X energy efficiency compared with ParaPIM on networks with 80% average sparsity.

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