基于实时的负载延迟跟踪的高效指令调度
Efficient Instruction Scheduling using Real-time Load Delay Tracking
摘要：
当今高性能乱序处理器中的许多硬件结构不能以有效的方式扩展。为了解决这个问题，已经提出了以节能方式构建执行调度的不同解决方案。发布时间预测处理器是这样一种解决方案，其使用数据流依赖性和预定义的指令延迟来预测重复指令的发布时间。在这项工作中，我们的目标是以节能的方式提高其准确性，从而提高其性能。我们通过利用两个关键的观察来实现这一点。首先，存储器访问通常需要比用于描述这些系统的静态预定义访问延迟更多的时间才能到达。其次，我们发现这些内存访问延迟经常在同一代码的迭代中重复。这反过来又使我们能够预测这些访问的到达时间。在这项工作中，我们引入了一个新的处理器微体系结构，取代了一个复杂的预约站为基础的调度与一个有效的，可扩展的替代方案。我们提出的调度技术跟踪负载的实时的【形】延迟，以准确地预测指令的发布时间，并使用一个重新排序机制，根据该预测优先处理指令，实现接近无序的处理器性能。为了以节能的方式实现这一点，我们引入：（1）指令延迟学习机制，监视重复的加载指令并学习它们的最新延迟，（2）发布时间预测器，使用学习的延迟和数据流依赖性来预测指令发布时间，以及（3）优先级队列，根据它们的发布时间预测对指令进行重新排序。总的来说，我们的处理器实现了传统无序处理器的86.2%的性能，高于以前的高效调度器建议，同时功耗仍然降低了30%。
英文摘要：
Many hardware structures in today's high-performance out-of-order processors do not scale in an efficient way. To address this, different solutions have been proposed that build execution schedules in an energy-efficient manner. Issue time prediction processors are one such solution that use data-flow dependencies and predefined instruction latencies to predict issue times of repeated instructions. In this work, we aim to improve their accuracy, and consequently their performance, in an energy efficient way. We accomplish this by taking advantage of two key observations. First, memory accesses often take additional time to arrive than the static, predefined access latency that is used to describe these systems. Second, we find that these memory access delays often repeat across iterations of the same code. This, in turn, allows us to predict the arrival time of these accesses. In this work, we introduce a new processor microarchitecture, that replaces a complex reservation-station-based scheduler with an efficient, scalable alternative. Our proposed scheduling technique tracks real-time delays of loads to accurately predict instruction issue times, and uses a reordering mechanism to prioritize instructions based on that prediction, achieving close-to-out-of-order processor performance. To accomplish this in an energy-efficient manner we introduce: (1) an instruction delay learning mechanism that monitors repeated load instructions and learns their latest delay, (2) an issue time predictor that uses learned delays and data-flow dependencies to predict instruction issue times and (3) priority queues that reorder instructions based on their issue time prediction. Together, our processor achieves 86.2% of the performance of a traditional out-of-order processor, higher than previous efficient scheduler proposals, while still consuming 30% less power.
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