Constable：通过安全消除加载指令执行来提升性能与功耗效率
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
AI总结：
提出纯微架构技术 Constable，通过动态识别并安全消除稳定加载指令的执行，同时缓解数据与资源依赖，显著提升性能并降低功耗。
摘要：
加载指令由于引发的数据和资源依赖，常常限制现代处理器中的指令级并行（ILP）。先前的技术如 Load Value Prediction (LVP) 和 Memory Renaming (MRN) 通过预测加载指令的数据值来缓解加载数据依赖。然而，由于预测的加载指令仍会被执行，它们未能缓解加载资源依赖。我们在本工作中的目标是通过缓解加载数据依赖和资源依赖来提升 ILP。为此，我们提出了一种纯微架构技术 Constable，能够安全消除加载指令的执行。Constable 动态识别那些反复从同一加载地址获取相同数据的加载指令。我们称此类加载为 likely-stable。对于每个 likely-stable 加载，Constable (1) 通过轻量级硬件结构追踪对其源架构寄存器和内存位置的修改，并 (2) 消除该加载指令后续实例的执行，直到其源寄存器发生写操作，或其加载地址收到存储或侦听请求。我们使用 90 种工作负载进行的广泛评估表明，在实现了 MRN 和其他动态指令优化（例如 move 和 zero elimination、constant 和 branch folding）的强基线系统上，Constable 平均提升性能 5.1%，同时降低核心动态功耗 3.4%。在存在 2-way simultaneous multithreading (SMT) 的情况下，Constable 相对基线系统的性能提升增至 8.8%。当与最先进的加载值预测器 (EVES) 结合时，在分别不启用和启用 2-way SMT 的基线系统中，Constable 相比单独使用该加载值预测器分别额外提供 3.7% 和 7.8% 的平均性能收益。
英文摘要：
Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction (LVP) and Memory Renaming (MRN) mitigate load data dependence by predicting the data value of a load instruction. However, they fail to mitigate load resource dependence as the predicted load instruction gets executed nonetheless. Our goal in this work is to improve ILP by mitigating both load data dependence and resource dependence. To this end, we propose a purely-microarchitectural technique called Constable, that safely eliminates the execution of load instructions. Constable dynamically identifies load instructions that have repeatedly fetched the same data from the same load address. We call such loads likely-stable. For every likely-stable load, Constable (1) tracks modifications to its source architectural registers and memory location via lightweight hardware structures, and (2) eliminates the execution of subsequent instances of the load instruction until there is a write to its source register or a store or snoop request to its load address. Our extensive evaluation using a wide variety of 90 workloads shows that Constable improves performance by 5.1% while reducing the core dynamic power consumption by 3.4% on average over a strong baseline system that implements MRN and other dynamic instruction optimizations (e.g., move and zero elimination, constant and branch folding). In presence of 2-way simultaneous multithreading (SMT), Constable's performance improvement increases to 8.8% over the baseline system. When combined with a state-of-the-art load value predictor (EVES), Constable provides an additional 3.7% and 7.8% average performance benefit over the load value predictor alone, in the baseline system without and with 2-way SMT, respectively.
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