高级finFET节点的数字存内计算
Analysing digital in-memory computing for advanced finFET node
摘要：
数字存内计算提高了数据密集型过程的能量效率和吞吐量，这会引起存储器颠簸，并导致冯诺依曼架构中的多个相同的存储器访问。数字存内计算涉及同时访问多个SRAM单元，这可能导致在不严格定时时发生位翻转。因此，我们讨论了在SRAM计算期间位线的瞬态电压特性。为了提高封装密度并避免MOSFET缩小尺寸问题，我们使用了7 nm预测PDK，该PDK使用finFET节点。finFET工艺具有分立鳍和较低的电压供应，这使得存储器内计算SRAM的设计变得困难。在本文中，我们设计了一个6 T SRAM单元在7纳米finFET节点，并比较其SNM与UMC 28纳米节点实现。此外，我们还设计和仿真了SRAM的其余外设，以及高级finFET节点的内存计算。
英文摘要：
Digital In-memory computing improves energy efficiency and throughput of a data-intensive process, which incur memory thrashing and, resulting multiple same memory accesses in a von Neumann architecture. Digital in-memory computing involves accessing multiple SRAM cells simultaneously, which may result in a bit flip when not timed critically. Therefore we discuss the transient voltage characteristics of the bitlines during an SRAM compute. To improve the packaging density and also avoid MOSFET down-scaling issues, we use a 7-nm predictive PDK which uses a finFET node. The finFET process has discrete fins and a lower Voltage supply, which makes the design of in-memory compute SRAM difficult. In this paper, we design a 6T SRAM cell in 7-nm finFET node and compare its SNMs with a UMC 28nm node implementation. Further, we design and simulate the rest of the SRAM peripherals, and in-memory computation for an advanced finFET node.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
