先进FinFET节点中的高性能低功耗绝热脉动阵列设计
High-Performance Low-Power Adiabatic Systolic Array Design in Advanced FinFET Nodes
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中文总结 AI 辅助
该研究针对先进FinFET节点的功耗限制，提出绝热逻辑设计方法，实现1 GHz下功耗较数字方案降42%/36%，可扩展至更先进节点以优化功耗性能。
中文摘要 AI 辅助
绝热逻辑传统上被视为一种低功耗解决方案，但为了维持绝热行为，其时钟速度受到限制。然而，对于先进FinFET节点而言，尽管器件本征速度持续按比例缩小，但受功耗/热问题（暗硅）影响，时钟频率已趋于平稳。这种情况为绝热逻辑在GHz级时钟下仍能维持绝热行为创造了机会。我们通过在商用16 nm FinFET工艺中实现的乘累加（MAC）脉动阵列，展示了一种绝热逻辑（AL）设计方法，该阵列包含谐振四相位功率时钟（PCK）发生器，以及数字-AL和AL-数字接口。仿真结果表明，与数字对应方案相比，该AL MAC脉动阵列在1 GHz下的核心功耗降低达42%，系统功耗降低达36%。向更先进节点扩展应能提供更优的功耗/性能指标。
英文摘要
Adiabatic logic has traditionally been recognized as a low-power solution but constrained to low clock speeds to preserve adiabatic behavior. For advanced FinFET nodes, however, clock frequencies have plateaued due to power/thermal concerns (dark silicon) even as the intrinsic device speeds have continued to scale. This convergence opens an opportunity for adiabatic logic to maintain adiabatic behavior even at GHz clocks. We demonstrate an adiabatic logic (AL) design methodology through a MAC systolic array implemented in commercial 16 nm FinFET technology with a resonant 4-phase power clock (PCK) generator, including digital-to-AL and AL-to-digital interfaces. Simulations show that the AL MAC systolic array at 1 GHz achieves power reductions of up to 42% and 36% at the core and system levels, respectively, compared to digital counterparts. Scaling to more advanced nodes should provide even better power/performance metrics.
发表机构
- University of Virginia（弗吉尼亚大学）
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