Machine learning (ML) is successful in achieving human-level performance in various fields. However, it lacks the ability to explain an outcome due to its black-box nature. While existing explainable ML is promising, almost all of these methods focus on formatting interpretability as an optimization problem. Such a mapping leads to numerous iterations of time-consuming complex computations, which limits their applicability in real-time applications. In this paper, we propose a novel framework for accelerating explainable ML using Tensor Processing Units (TPUs). The proposed framework exploits the synergy between matrix convolution and Fourier transform, and takes full advantage of TPU's natural ability in accelerating matrix computations. Specifically, this paper makes three important contributions. (1) To the best of our knowledge, our proposed work is the first attempt in enabling hardware acceleration of explainable ML using TPUs. (2) Our proposed approach is applicable across a wide variety of ML algorithms, and effective utilization of TPU-based acceleration can lead to real-time outcome interpretation. (3) Extensive experimental results demonstrate that our proposed approach can provide an order-of-magnitude speedup in both classification time (25x on average) and interpretation time (13x on average) compared to state-of-the-art techniques.
Amazon Quantum Solutions Lab（亚马逊量子解决方案实验室）；AWS Center for Quantum Computing（AWS量子计算中心）；California Institute of Technology（加州理工学院）；Fidelity Center for Applied Technology, FMR LLC（FMR有限责任公司富达应用技术中心）；AI Center of Excellence, FMR LLC（FMR有限责任公司人工智能卓越中心）
MC$^2$A: Enabling Algorithm-Hardware Co-Design for Efficient Markov Chain Monte Carlo Acceleration
Department of Electrical Engineering - MICAS, KU Leuven, Belgium（电气工程系-MICAS，卢森堡大学）；Department of Computer Science - DTAI, KU Leuven, Belgium（计算机科学系-DTAI，卢森堡大学）；Department of Electronics and Nanoengineering, Aalto University（电子与纳米工程系，阿alto大学）
Qibo: a framework for quantum simulation with hardware acceleration
Quantum Research Centre, Technology Innovation Institute（技术创新研究院量子研究中心）；Departament de Física Quàntica i Astrofísica and Institut de Ciències del Cosmos (ICCUB), Universitat de Barcelona（巴塞罗那大学量子物理与天体物理系及宇宙科学研究所）；Barcelona Supercomputing Center（巴塞罗那超级计算中心）；Instituto de Física Teórica, UAM-CSIC（马德里自治大学-西班牙高等科学研究理事会理论物理研究所）；Qilimanjaro Quantum Tech（Qilimanjaro量子科技公司）；Centre for Quantum Technologies, National University of Singapore（新加坡国立大学量子技术中心）
Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights
School of Computing Informatics and Decision Systems Engineering at Arizona State University（亚利桑那州立大学计算、信息科学与工程学院）；Computer Science and Artificial Intelligence Laboratory at Massachusetts Institute of Technology（麻省理工学院计算机科学与人工智能实验室）；School of Computer Science at University of California, Los Angeles（加利福尼亚大学洛杉矶分校计算机科学学院）；Parallel Computing Lab at Intel Labs（英特尔实验室并行计算实验室）
Explainable and Hardware-Efficient Jamming Detection for 5G Networks Using the Convolutional Tsetlin Machine
Center of Artificial Intelligence Research, University of Agder（人工智能研究中心，阿格德大学）；University of Agder（阿格德大学）；School of Electrical Engineering and Computer Science, University of Ottawa（电气工程与计算机科学学院，渥太华大学）
To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration
Politecnico di Torino（都灵理工大学）；Delft University of Technology（代尔夫特理工大学）；University of Zürich and ETH Zürich（苏黎世大学和苏黎世联邦理工学院）；University of California Santa Cruz（加州大学圣克鲁兹分校）
Enabling Physical AI at the Edge: Hardware-Accelerated Recovery of System Dynamics
School of Electrical Engineering Arizona State University Tempe, USA（电气工程学院亚利桑那州立大学Tempe分校）；School of Computing Science Arizona State University Tempe, USA（计算科学学院亚利桑那州立大学Tempe分校）
FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Review
Key Laboratory of Low-Dimensional Quantum Structures and Quantum Control of Ministry of Education, School of Physics and Electronics, Hunan Normal University（教育部低维量子结构与量子控制重点实验室，物理电子学院，湖南师范大学）
Computer Systems Lab, Cornell University（康奈尔大学计算机系统实验室）；Systems and Networking Research Group, Microsoft Research（微软研究院系统与网络研究组）；Department of Electrical and Electronic Engineering, Imperial College London（伦敦帝国理工学院电子与电气工程系）
Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Northeastern University（东北大学）；Simon Fraser University（西蒙弗雷泽大学）；University of California, Irvine（加州大学欧文分校）；ETH Zurich（苏黎世联邦理工学院）；The University of Texas at Austin（德克萨斯大学奥斯汀分校）
视觉Transformer（ViT）正在出现，在计算机视觉任务中具有显著提高的准确性。然而，其复杂的体系结构和巨大的计算/存储需求迫切需要新的硬件加速器的设计方法。这项工作提出了一个FPGA感知的自动ViT加速框架的基础上提出的混合方案量化。据我们所知，这是第一个基于FPGA的ViT加速框架，探索模型量化。与最先进的ViT量化工作（算法方法，只有没有硬件加速）相比，我们的量化实现了0.47%至1.36%的高的Top-1精度在相同的位宽。与32位浮点基线FPGA加速器相比，我们的加速器的帧速率提高了约5.6倍（即，56.8 FPS vs. 10.0 FPS），DeiT-base在ImageNet数据集上的准确率下降了0.71%。
hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware
Purdue University（普渡大学）；ETH Zurich（苏黎世联邦理工学院）；California Institute of Technology（加州理工学院）；Fermi National Accelerator Lab（费米国家加速器实验室）；European Organization for Nuclear Research (CERN)（欧洲核子研究中心）；University of California San Diego（加州大学圣地亚哥分校）；Imperial College London（伦敦帝国理工学院）；National Technical University of Athens（希腊国家技术大学）；University of Geneva（日内瓦大学）；Altera Corporation（阿尔特拉公司）；Discovery Partners Institute（发现伙伴研究所）；Massachusetts Institute of Technology（麻省理工学院）；National Yang Ming Chiao Tung University（国立阳明交通大学）；Northwestern University（西北大学）；Princeton University（普林斯顿大学）；University of Illinois Urbana-Champaign（伊利诺伊大学厄巴纳-香槟分校）；University of Michigan（密歇根大学）；University of Pennsylvania（宾夕法尼亚大学）；University of Washington（华盛顿大学）
