arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2102.06326cs.LOcs.ARcs.FL
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基于形式化模型检验的高级延迟不敏感设计

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking

Steve Dai, Alicia Klinefelter, Haoxing Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Pinckney, Brucek Khailany

摘要:

延迟不敏感设计可缓解互连延迟的增加,并在复杂的数字系统中实现高效的组件重用。这种设计风格已经在高级设计流程中采用,因为通过延迟不敏感接口连接的不定时功能块提供了自然的通信抽象。然而,使用高级语言的延迟不敏感设计也引入了一组独特的验证挑战,这些挑战危及功能正确性。特别是,由于输入的无效消耗和死锁导致的错误可能难以用动态仿真方法检测和调试。为了解决这两类错误,我们提出了正式的模型检验方法,以保证高层次的延迟不敏感的设计不受无效的输入数据,是免费的死锁。我们为每个属性开发了一个结构良好的验证包装器,以自动构建相应的形式化模型进行检查。我们的实验表明,正式检查是有效的,在现实的错误场景从高层次的设计。

英文摘要:

Latency-insensitive design mitigates increasing interconnect delay and enables productive component reuse in complex digital systems. This design style has been adopted in high-level design flows because untimed functional blocks connected through latency-insensitive interfaces provide a natural communication abstraction. However, latency-insensitive design with high-level languages also introduces a unique set of verification challenges that jeopardize functional correctness. In particular, bugs due to invalid consumption of inputs and deadlocks can be difficult to detect and debug with dynamic simulation methods. To tackle these two classes of bugs, we propose formal model checking methods to guarantee that a high-level latency-insensitive design is unaffected by invalid input data and is free of deadlock. We develop a well-structured verification wrapper for each property to automatically construct the corresponding formal model for checking. Our experiments demonstrate that the formal checks are effective in realistic bug scenarios from high-level designs.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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