ANDROMEDA：一种基于FPGA的RISC-V MPSoC探索框架
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework
摘要：
随着消费电子产品需求的不断增长，计算需求呈指数级增长。由于应用程序的计算需求，计算机架构师正试图在单个管芯上封装尽可能多的核以加速应用程序代码的执行。在多处理器片上系统（MPSoC）中，在内核数量、存储器子系统和片上网络参数之间取得平衡对于获得期望的性能是至关重要的。在本文中，我们提出了ANDROMEDA，一个基于RISC-V的框架，使我们能够探索MPSoC的不同配置，并观察性能的损失和收益。我们在Synopsys HAPS-80 D Dual FPGA平台上仿真了MPSoC的各种配置。使用STREAM，矩阵乘法和N体模拟作为基准，我们证明了我们的框架的有效性，快速确定正确的参数，有效地执行这些基准。
英文摘要：
With the growing demands of consumer electronic products, the computational requirements are increasing exponentially. Due to the applications' computational needs, the computer architects are trying to pack as many cores as possible on a single die for accelerated execution of the application program codes. In a multiprocessor system-on-chip (MPSoC), striking a balance among the number of cores, memory subsystems, and network-on-chip parameters is essential to attain the desired performance. In this paper, we present ANDROMEDA, a RISC-V based framework that allows us to explore the different configurations of an MPSoC and observe the performance penalties and gains. We emulate the various configurations of MPSoC on the Synopsys HAPS-80D Dual FPGA platform. Using STREAM, matrix multiply, and N-body simulations as benchmarks, we demonstrate our framework's efficacy in quickly identifying the right parameters for efficient execution of these benchmarks.
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