Low-latency, low-power portable recurrent neural network (RNN) accelerators offer powerful inference capabilities for real-time applications such as IoT, robotics, and human-machine interaction. We propose a lightweight Gated Recurrent Unit (GRU)-based RNN accelerator called EdgeDRNN that is optimized for low-latency edge RNN inference with batch size of 1. EdgeDRNN adopts the spiking neural network inspired delta network algorithm to exploit temporal sparsity in RNNs. Weights are stored in inexpensive DRAM which enables EdgeDRNN to compute large multi-layer RNNs on the most inexpensive FPGA. The sparse updates reduce DRAM weight memory access by a factor of up to 10x and the delta can be varied dynamically to trade-off between latency and accuracy. EdgeDRNN updates a 5 million parameter 2-layer GRU-RNN in about 0.5ms. It achieves latency comparable with a 92W Nvidia 1080 GPU. It outperforms NVIDIA Jetson Nano, Jetson TX2 and Intel Neural Compute Stick 2 in latency by 5X. For a batch size of 1, EdgeDRNN achieves a mean effective throughput of 20.2GOp/s and a wall plug power efficiency that is over 4X higher than the commercial edge AI platforms.
Adaptive Robotic Arm Control with a Spiking Recurrent Neural Network on a Digital Accelerator
University of Sevilla（塞维利亚大学）；Politecnico di Torino（都灵理工大学）；Graz University of Technology（格拉茨工业大学）；University of Zurich（苏黎世大学）；Delft University of Technology（代尔夫特理工大学）
Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
Department of Computer and Control Engineering（计算机与控制工程系）；Politecnico di Torino（托尼诺理工大学）；Interuniversity Department of Regional and Urban Studies and Planning（区域与城市研究和规划联合大学部门）
DPD-NeuralEngine: A 22-nm 6.6-TOPS/W/mm$^2$ Recurrent Neural Network Accelerator for Wideband Power Amplifier Digital Pre-Distortion
Department of Microelectronics, Delft University of Technology, The Netherlands（代尔夫特理工大学微电子系）；Leiden Institute of Advanced Computer Science (LIACS), Leiden University, The Netherlands（莱顿大学先进计算机科学研究所）
Optimizing Temporal Convolutional Network inference on FPGA-based accelerators
卷积神经网络广泛应用于各种应用中，通常包括图像和视频分类、识别和分割等计算机视觉任务。最近的研究结果表明，涉及一维卷积和膨胀的多层（深度）网络可以有效地用于时间序列和序列分类和分割，以及涉及序列建模的任务。这些结构通常被称为时间卷积网络（TCN），已被证明在准确性和训练时间方面始终优于递归神经网络[1]。虽然基于FPGA的经典CNN推理加速器很普遍，但文献缺乏对TCN模型推理可用性的定量评估。在本文中，我们提出了这样的评估，考虑到CNN加速器的特定功能，支持TCN内核作为参考和一组最先进的TCN作为基准。实验结果表明，在TCN执行过程中，操作强度对整体性能至关重要。我们提出了一种基于批处理的卷积调度，可以将效率提高到理论峰值性能的96%。总体而言，我们可以在Ultrascale+ ZU 3EG上实现高达111.8 GOPS/s和33.9 GOPS/s/W的功率效率（相对于纯软件实现，加速高达10倍，功率效率提高3倍）。
A Runtime-Adaptive Transformer Neural Network Accelerator on FPGAs
Department of Electrical Engineering and Computer Science, University of Arkansas（电气工程与计算机科学系，亚拉巴马大学）；Department of Computer Science and Engineering, University of South Carolina（计算机科学与工程系，南卡罗来纳大学）
AIGOR: A Modular, Event-Driven Neuromorphic Architecture for Configurable SNN Inference
Istituto Nazionale di Fisica Nucleare, Sezione di Roma（意大利国家核物理研究所罗马分部）；Istituto Nazionale di Fisica Nucleare, Sezione di Roma Tor Vergata（意大利国家核物理研究所罗马托尔维加塔分部）；Università Sapienza di Roma（罗马大学）
