基于FPGA加速器的时间卷积网络推理优化
Optimizing Temporal Convolutional Network inference on FPGA-based accelerators
摘要：
卷积神经网络广泛应用于各种应用中，通常包括图像和视频分类、识别和分割等计算机视觉任务。最近的研究结果表明，涉及一维卷积和膨胀的多层（深度）网络可以有效地用于时间序列和序列分类和分割，以及涉及序列建模的任务。这些结构通常被称为时间卷积网络（TCN），已被证明在准确性和训练时间方面始终优于递归神经网络[1]。虽然基于FPGA的经典CNN推理加速器很普遍，但文献缺乏对TCN模型推理可用性的定量评估。在本文中，我们提出了这样的评估，考虑到CNN加速器的特定功能，支持TCN内核作为参考和一组最先进的TCN作为基准。实验结果表明，在TCN执行过程中，操作强度对整体性能至关重要。我们提出了一种基于批处理的卷积调度，可以将效率提高到理论峰值性能的96%。总体而言，我们可以在Ultrascale+ ZU 3EG上实现高达111.8 GOPS/s和33.9 GOPS/s/W的功率效率（相对于纯软件实现，加速高达10倍，功率效率提高3倍）。
英文摘要：
Convolutional Neural Networks are extensively used in a wide range of applications, commonly including computer vision tasks like image and video classification, recognition, and segmentation. Recent research results demonstrate that multilayer(deep) networks involving mono-dimensional convolutions and dilation can be effectively used in time series and sequences classification and segmentation, as well as in tasks involving sequence modelling. These structures, commonly referred to as Temporal Convolutional Networks (TCNs), have been demonstrated to consistently outperform Recurrent Neural Networks in terms of accuracy and training time [1]. While FPGA-based inference accelerators for classic CNNs are widespread, literature is lacking in a quantitative evaluation of their usability on inference for TCN models. In this paper we present such an evaluation, considering a CNN accelerator with specific features supporting TCN kernels as a reference and a set of state-of-the-art TCNs as a benchmark. Experimental results show that, during TCN execution, operational intensity can be critical for the overall performance. We propose a convolution scheduling based on batch processing that can boost efficiency up to 96% of theoretical peak performance. Overall we can achieve up to 111,8 GOPS/s and power efficiency of 33,9 GOPS/s/W on an Ultrascale+ ZU3EG (up to 10x speedup and 3x power efficiency improvement with respect to pure software implementation).
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
