Decision trees are machine learning models commonly used in various application scenarios. In the era of big data, traditional decision tree induction algorithms are not suitable for learning large-scale datasets due to their stringent data storage requirement. Online decision tree learning algorithms have been devised to tackle this problem by concurrently training with incoming samples and providing inference results. However, even the most up-to-date online tree learning algorithms still suffer from either high memory usage or high computational intensity with dependency and long latency, making them challenging to implement in hardware. To overcome these difficulties, we introduce a new quantile-based algorithm to improve the induction of the Hoeffding tree, one of the state-of-the-art online learning models. The proposed algorithm is light-weight in terms of both memory and computational demand, while still maintaining high generalization ability. A series of optimization techniques dedicated to the proposed algorithm have been investigated from the hardware perspective, including coarse-grained and fine-grained parallelism, dynamic and memory-based resource sharing, pipelining with data forwarding. We further present a high-performance, hardware-efficient and scalable online decision tree learning system on a field-programmable gate array (FPGA) with system-level optimization techniques. Experimental results show that our proposed algorithm outperforms the state-of-the-art Hoeffding tree learning method, leading to 0.05% to 12.3% improvement in inference accuracy. Real implementation of the complete learning system on the FPGA demonstrates a 384x to 1581x speedup in execution time over the state-of-the-art design.
FTRANS: Energy-Efficient Acceleration of Transformers using FPGA
University of Connecticut（康涅狄格大学）；Stevens Institute of Technology（斯蒂文斯理工学院）；Syracuse University（雪城大学）；Microsoft Corporation（微软公司）；Oak Ridge National Laboratory（橡树岭国家实验室）；University of Texas at San Antonio（德克萨斯大学圣安东尼奥分校）
Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Northeastern University（东北大学）；Simon Fraser University（西蒙弗雷泽大学）；University of California, Irvine（加州大学欧文分校）；ETH Zurich（苏黎世联邦理工学院）；The University of Texas at Austin（德克萨斯大学奥斯汀分校）
视觉Transformer（ViT）正在出现，在计算机视觉任务中具有显著提高的准确性。然而，其复杂的体系结构和巨大的计算/存储需求迫切需要新的硬件加速器的设计方法。这项工作提出了一个FPGA感知的自动ViT加速框架的基础上提出的混合方案量化。据我们所知，这是第一个基于FPGA的ViT加速框架，探索模型量化。与最先进的ViT量化工作（算法方法，只有没有硬件加速）相比，我们的量化实现了0.47%至1.36%的高的Top-1精度在相同的位宽。与32位浮点基线FPGA加速器相比，我们的加速器的帧速率提高了约5.6倍（即，56.8 FPS vs. 10.0 FPS），DeiT-base在ImageNet数据集上的准确率下降了0.71%。
FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Review
Key Laboratory of Low-Dimensional Quantum Structures and Quantum Control of Ministry of Education, School of Physics and Electronics, Hunan Normal University（教育部低维量子结构与量子控制重点实验室，物理电子学院，湖南师范大学）
BearingPGA-Net: A Lightweight and Deployable Bearing Fault Diagnosis Network via Decoupled Knowledge Distillation and FPGA Acceleration
Harbin Institute of Technology（哈尔滨工业大学）；The Hong Kong Polytechnic University（香港理工大学）；Analog Devices, Inc.（亚德诺公司）；The Chinese University of Hong Kong（香港中文大学）
Binary Complex Neural Network Acceleration on FPGA
University of Connecticut（康涅狄格大学）；Stevens Institute of Technology（史蒂文斯理工学院）；University of Texas at San Antonio（德克萨斯大学圣安东尼奥分校）；Pacific Northwest National Laboratory（太平洋西北国家实验室）
