Rapid design space exploration in early design stage is critical to algorithm-architecture co-design for accelerators. In this work, a pre-RTL cycle-accurate accelerator simulator based on SystemC transaction-level modeling (TLM), AccTLMSim, is proposed for convolutional neural network (CNN) accelerators. The accelerator simulator keeps track of each bus transaction between accelerator and DRAM, taking into account the communication bandwidth. The simulation results are validated against the implementation results on the Xilinx Zynq. Using the proposed simulator, it is shown that the communication bandwidth is severely affected by DRAM latency and bus protocol overhead. In addition, the loop tiling is optimized to maximize the performance under the constraint of on-chip SRAM size. Furthermore, a new performance estimation model is proposed to speed up the design space exploration. Thanks to the proposed simulator and performance estimation model, it is possible to explore a design space of millions of architectural options within a few tens of minutes.
Beacon: LLM Multi-Agent Driven Hardware Design Space Exploration for Heterogeneous Multi-Chiplet Deep Learning Accelerators
University of Science and Technology of China（中国科学技术大学）；Suzhou Institute for Advanced Research, University of Science and Technology of China（中国科学技术大学苏州高等研究院）
ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression
State Key Laboratory of Processors, Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所处理器重点实验室）；University of Chinese Academy of Sciences（中国科学院大学）；CASTEST Co., Ltd.（思立特科技有限公司）；Zijing Xinjie Intelligent Technology Co., Ltd.（紫晶新捷智能科技有限公司）
DCO: Dynamic Cache Orchestration for LLM Accelerators through Predictive Management
Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology（电子与计算机工程系，香港科学与技术大学）；School of Electronic Science and Engineering, Southeast University（电子科学与工程学院，东南大学）
Systematic Exploration of Multi-core Architectures for Efficient LLM Serving using WaferAI-SIM
Institute of Parallel and Distributed Systems, Shanghai Jiao Tong University（上海交通大学平行与分布式系统研究所）；Department of Precision Instrument, Tsinghua University（清华大学精密仪器系）
ACALSim: A Scalable Parallel Simulation Framework for High-Performance System Design Space Exploration
Mijotech Inc.（Mijotech公司）；Taiwan High-Performance Computing Education Association（台湾高性能计算教育协会）；National Cheng Kung University（国立成功大学）；National Yang Ming Chiao Tung University（国立阳明交通大学）
EdgeCIM: A Hardware-Software Co-Design for CIM-Based Acceleration of Small Language Models
King Abdullah University of Science and Technology（阿卜杜拉国王科技大学）；University of California Irvine（加利福尼亚大学尔湾分校）；Rain Neuromorphics Inc.（Rain Neuromorphics公司）
