arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2005.08183cs.CRcs.AR
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一种轻量级安全分支预测器隔离机制

A Lightweight Isolation Mechanism for Secure Branch Predictors

Lutan Zhao, Peinan Li, Rui Hou, Michael C. Huang, Jiazhen Li, Lixin Zhang, Xuehai Qian, Dan Meng

摘要:

最近暴露的漏洞揭示了提高分支预测器安全性的必要性。分支预测器记录不同程序的执行历史,来自不同进程的这些信息存储在同一结构中,因此可以相互访问。这给攻击者留下了恶意训练和恶意感知的机会。我们不想对硬件资源进行基于刷新或物理隔离,而是希望通过使用随机化的一些轻量级处理来实现这些硬件表中内容的隔离,如下所示。(1)内容编码.我们建议使用基于硬件的线程私有随机数来编码分支预测器表(方向和目的地历史)的内容,我们称之为XOR-BP。具体地,数据在写入表中之前通过与密钥的XOR操作进行编码,并且在从表中读取之后进行解码。这种机制混淆了信息,增加了跨进程或跨特权级别分析和感知的困难。它实现了类似的逻辑隔离效果,但在空间或时间开销方面几乎没有增加。(2)索引编码。我们提出了一种分支预测器的随机索引机制(Noisy-XOR-BP)。类似于XOR-BP,另一个线程私有随机数与分支指令地址一起用作计算分支预测器的索引的输入。这种随机化索引机制破坏了分支指令地址和分支预测器条目之间的对应关系,从而增加了恶意感知攻击的噪声。我们使用基于FPGA的RISC-V处理器原型和额外的辅助模拟进行的分析表明,所提出的机制在提供强大保护的同时会产生非常小的性能成本。

英文摘要:

Recently exposed vulnerabilities reveal the necessity to improve the security of branch predictors. Branch predictors record history about the execution of different programs, and such information from different processes are stored in the same structure and thus accessible to each other. This leaves the attackers with the opportunities for malicious training and malicious perception. Instead of flush-based or physical isolation of hardware resources, we want to achieve isolation of the content in these hardware tables with some lightweight processing using randomization as follows. (1) Content encoding. We propose to use hardware-based thread-private random numbers to encode the contents of the branch predictor tables (both direction and destination histories) which we call XOR-BP. Specifically, the data is encoded by XOR operation with the key before written in the table and decoded after read from the table. Such a mechanism obfuscates the information adding difficulties to cross-process or cross-privilege level analysis and perception. It achieves a similar effect of logical isolation but adds little in terms of space or time overheads. (2) Index encoding. We propose a randomized index mechanism of the branch predictor (Noisy-XOR-BP). Similar to the XOR-BP, another thread-private random number is used together with the branch instruction address as the input to compute the index of the branch predictor. This randomized indexing mechanism disrupts the correspondence between the branch instruction address and the branch predictor entry, thus increases the noise for malicious perception attacks. Our analyses using an FPGA-based RISC-V processor prototype and additional auxiliary simulations suggest that the proposed mechanisms incur a very small performance cost while providing strong protection.

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