欠搭接MoS $_2$场效应晶体管的电可调室温磁滞渡越
Electrically Tunable Room Temperature Hysteresis Crossover in Underlap MoS$_2$ FETs
摘要：
具有石墨烯和MoS $_2$沟道的场效应晶体管（FET）的电流-电压传输特性中的顺时针到逆时针滞后交叉对于非易失性存储器应用具有重要的前景。然而，这样的交叉已被证明只在高温下表现出来。在这项工作中，第一次，我们证明了室温滞后交叉在几层的MoS $_2$场效应晶体管通过使用栅极-漏极欠搭接设计诱导的差分响应，从陷阱在MoS $_2$ -HfO $_2$沟道栅电介质界面施加栅极偏置。在欠重叠FET中在高栅极电压下界面陷阱驱动的逆时针滞后的出现可以明确地归因于欠重叠的存在，因为具有和不具有欠重叠区域的晶体管被制造在相同的MoS $_2$沟道薄片上。下重叠设计还使得能够利用施加的漏极偏压和下重叠长度对逆时针滞后窗口（通过140 $\times$）以及交叉栅极电压（通过2.6 $\times$）进行室温调谐。在环境和真空条件下，在不同的扫描速率和温度（RT，45 $^\circ$ C和65 $^\circ$ C）的传输曲线的综合测量有助于隔离的吸附质，界面陷阱，和散装HfO $_2$陷阱的顺时针和逆时针滞后的定量贡献。
英文摘要：
Clockwise to anti-clockwise hysteresis crossover in current-voltage transfer characteristics of field effect transistors (FETs) with graphene and MoS$_2$ channels holds significant promise for non-volatile memory applications. However such crossovers have been shown to manifest only at high temperature. In this work, for the first time, we demonstrate room temperature hysteresis crossover in few-layer MoS$_2$ FETs by using a gate-drain underlap design to induce a differential response from traps at the MoS$_2$-HfO$_2$ channel-gate dielectric interface to applied gate bias. The appearance of interface trap-driven anti-clockwise hysteresis at high gate voltages in underlap FETs can be unambiguously attributed to the presence of an underlap since transistors with and without the underlap region were fabricated on the same MoS$_2$ channel flake. The underlap design also enables room temperature tuning of the anti-clockwise hysteresis window (by 140$\times$) as well as the crossover gate voltage (by 2.6$\times$) with applied drain bias and underlap length. Comprehensive measurements of the transfer curves in ambient and vacuum conditions at varying sweep rates and temperatures (RT, 45 $^\circ$C and 65 $^\circ$C) help segregate the quantitative contributions of adsorbates, interface traps, and bulk HfO$_2$ traps to the clockwise and anti-clockwise hysteresis.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
