PMEvo：基于演化优化的无序处理器端口映射可移植推理
PMEvo: Portable Inference of Port Mappings for Out-of-Order Processors by Evolutionary Optimization
摘要：
在计算机系统中实现峰值性能需要在系统的每一层中进行优化，无论是硬件还是软件。详细了解底层硬件，尤其是处理器，对于优化软件至关重要。处理器性能的一个关键标准是它利用指令级并行的能力。这种能力是由处理器的端口映射决定的，端口映射描述了处理器对每条指令的执行单元。处理器制造商通常不共享其微体系结构的端口映射。虽然存在从实验中自动推断端口映射的方法，但它们基于特定于处理器的硬件性能计数器，这些计数器并不适用于每个平台。我们提出了PMEvo，一个框架来自动推断端口映射的基础上测量的短指令序列的执行时间。PMEvo使用一种进化算法，该算法使用线性规划的分析吞吐量模型来评估候选映射的适应度。我们的原型实现推断英特尔的Skylake架构，预测测量的指令吞吐量的准确性，是有竞争力的现有工作的端口映射。此外，它还找到了AMD Zen+架构和ARM Cortex-A72架构的端口映射，这些都超出了现有技术的范围。
英文摘要：
Achieving peak performance in a computer system requires optimizations in every layer of the system, be it hardware or software. A detailed understanding of the underlying hardware, and especially the processor, is crucial to optimize software. One key criterion for the performance of a processor is its ability to exploit instruction-level parallelism. This ability is determined by the port mapping of the processor, which describes the execution units of the processor for each instruction. Processor manufacturers usually do not share the port mappings of their microarchitectures. While approaches to automatically infer port mappings from experiments exist, they are based on processor-specific hardware performance counters that are not available on every platform. We present PMEvo, a framework to automatically infer port mappings solely based on the measurement of the execution time of short instruction sequences. PMEvo uses an evolutionary algorithm that evaluates the fitness of candidate mappings with an analytical throughput model formulated as a linear program. Our prototype implementation infers a port mapping for Intel's Skylake architecture that predicts measured instruction throughput with an accuracy that is competitive to existing work. Furthermore, it finds port mappings for AMD's Zen+ architecture and the ARM Cortex-A72 architecture, which are out of scope of existing techniques.
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