arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2003.06310eess.SPcs.ARcs.CVcs.NE

A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification

National Tsing Hua University(国立清华大学);National Cheng Kung University(国立成功大学);Industrial Technology Research Institute(工业技术研究院)

Pai-Yu Tan, Po-Yao Chuang, Yen-Ting Lin, Cheng-Wen Wu, Juin-Ming Lu

英文摘要:

Neural network hardware is considered an essential part of future edge devices. In this paper, we propose a binary-weight spiking neural network (BW-SNN) hardware architecture for low-power real-time object classification on edge platforms. This design stores a full neural network on-chip, and hence requires no off-chip bandwidth. The proposed systolic array maximizes data reuse for a typical convolutional layer. A 5-layer convolutional BW-SNN hardware is implemented in 90nm CMOS. Compared with state-of-the-art designs, the area cost and energy per classification are reduced by 7$\times$ and 23$\times$, respectively, while also achieving a higher accuracy on the MNIST benchmark. This is also a pioneering SNN hardware architecture that supports advanced CNN architectures.

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