We propose a new digital-to-analog converter (DAC) for realizing a synapse circuit of mixed-signal spiking neural networks. We named this circuit "time-domain DAC (TDAC)". This produces weights for converting a digital input code into voltage using one current waveform. Therefore, a TDAC is more compact than a conventional DAC that comprises many current sources and resistors. Moreover, a TDAC with leak resistance reproduces biological plausible synaptic responses that are expressed as alpha functions or dual exponential equations. We will show numerical analysis results of a TDAC and circuit simulation results of a circuit designed by the TSMC 40 nm CMOS process.
The level crossing analog-to-digital converters are meant for the effective conversion of sparse signals by construction. In these converters, the bandwidth-power trade-off requires a re-design of the comparators which takes a lot of time and effort to reach the application optimum point. Inspired by synchronous converters that have a dynamic power component that can be traded with bandwidth with the change of a clock frequency, a technique to allow such trade-off in the level crossing converter was developed. The resulting level crossing ADC has an input signal dependent dynamic power which c…
Typical bio-signal processing front-ends are designed to maximize the quality of the recorded data, to allow faithful reproduction of the signal for monitoring and off-line processing. This leads to designs that have relatively large area and power consumption figures. However, wearable devices for always-on biomedical applications do not necessarily require to reproduce highly accurate recordings of bio-signals, provided their end-to-end classification or anomaly detection performance is not compromised. Within this context, we propose an adaptive Asynchronous Delta Modulator (ADM) circuit de…
Based on an equivalent model for quantizers with noisy inputs recently presented in [35], we propose a method of digital dithering at the transmitter that may significantly reduce the resolution requirements of MIMO downlink Digital to Analog Convertors (DAC). We use this equivalent model to analyze the effect of the dither Probability Density Function (PFD), and show that the uniform PDF produces an optimal (linear) result. Relative to other methods of DAC quantization error reduction our approach has the benefits of low computational complexity, compatibility with all existing standards, and…
As the bridge between the analog world and digital computers, analog-to-digital converters are generally used in modern information systems such as radar, surveillance, and communications. For the configuration of analog-to-digital converters in future high-frequency broadband systems, we introduce a revolutionary architecture that adopts deep learning technology to overcome tradeoffs between bandwidth, sampling rate, and accuracy. A photonic front-end provides broadband capability for direct sampling and speed multiplication. Trained deep neural networks learn the patterns of system defects, …
In this paper, an on-chip photonic sampled and quantized analog-to-digital converter (ADC) on thin-film lithium niobate platform is experimentally demonstrated. Using two phase modulators as a sampler and a 5$\times$5 multimode interference (MMI) coupler as a quantizer, an 1 GHz sinusoidal analog input signal was successfully converted to a digitized output with a 20 GSample/s sampling rate. To evaluate the system performance, the quantization curves together with the transfer function of the ADC were measured. The experimental effective number of bits (ENOB) was 3.17 bit. The demonstrated dev…
This paper presents a dynamic predictive sampling (DPS) based analog-to-digital converter (ADC) that provides a non-uniform sampling of input analog continuous-time signals. The processing unit generates a dynamic prediction of the input signal using two prior-quantized samplings to compute digital values of an upper threshold and a lower threshold. The digital threshold values are converted to analog thresholds to form a tracking window. A comparator compares the input analog signal with the tracking window to determine if the prediction is successful. A counter records timestamps between the…
Based on a new equivalent model of quantizer with noisy input recently presented in [23], we propose a new low complexity receiver that takes into account the nonlinear distortion (NLD) generated by Analog to Digital converter (ADC) with insufficient resolution. The strength of new model is that it presents the NLD as a function of only the desired part of input signal (without noise). Therefore it can easily be used in a variety of NLD mitigation techniques. Here, as an illustration of this, we use a pseudo-ML approach to detect the original QAM modulation based on the equivalent transfer fun…
Digital-to-analog converters (DAC) are indispensable functional units in signal processing instrumentation and wide-band telecommunication links for both civil and military applications. Since photonic systems are capable of high data throughput and low latency, an increasingly found system limitation stems from the required domain-crossing such as digital-to-analog, and electronic-to-optical. A photonic DAC implementation, in contrast, enables a seamless signal conversion with respect to both energy efficiency and short signal delay, often require bulky discrete optical components and electri…
With the advent of the 5G wireless networks, achieving tens of gigabits per second throughputs and low, milliseconds, latency has become a reality. This level of performance will fuel numerous real-time applications, such as autonomy and augmented reality, where the computationally heavy tasks can be performed in the cloud. The increase in the bandwidth along with the use of dense constellations places a significant burden on the speed and accuracy of analog-to-digital converters (ADC). A popular approach to create wideband ADCs is utilizing multiple channels each operating at a lower speed in…
In a growing number of applications, there is a need to digitize signals whose spectral characteristics are challenging for traditional Analog-to-Digital Converters (ADCs). Examples, among others, include systems where the ADC must acquire at once a very wide but sparsely and dynamically occupied bandwidth supporting diverse services, as well as systems where the signal of interest is subject to strong narrowband co-channel interference. In such scenarios, the resolution requirements can be prohibitively high. As an alternative, the recently proposed modulo-ADC architecture can in principle re…
This paper focuses on channel estimation for mmWave MIMO systems with 1-bit spatial sigma-delta analog-to-digital converters (ADCs). The channel estimation performance with 1-bit spatial sigma-delta ADCs depends on the quantization noise modeling. Therefore, we present a new method for modeling the quantization noise by leveraging the deterministic input-output relation of the 1-bit spatial sigma-delta ADC. Using this new noise model, we propose an algorithm for channel estimation for a narrowband single-user mmWave line-of-sight MIMO system by determining the unknown angles and path attenuati…
Spiking Neural Networks (SNNs) can unleash the full power of analog Resistive Random Access Memories (RRAMs) based circuits for low power signal processing. Their inherent computational sparsity naturally results in energy efficiency benefits. The main challenge implementing robust SNNs is the intrinsic variability (heterogeneity) of both analog CMOS circuits and RRAM technology. In this work, we assessed the performance and variability of RRAM-based neuromorphic circuits that were designed and fabricated using a 130\,nm technology node. Based on these results, we propose a Neuromorphic Hardwa…
The increased power consumption of high-resolution data converters at higher carrier frequencies and larger bandwidths is becoming a bottleneck for communication systems. In this paper, we consider a fully digital base station equipped with 1-bit analog-to-digital (in uplink) and digital-to-analog (in downlink) converters on each radio frequency chain. The base station communicates with multiple single antenna users with individual SINR constraints. We first establish the uplink downlink duality principle under 1-bit hardware constraints under an uncorrelated quantization noise assumption. We …
Neuromorphic computing implementing spiking neural networks (SNN) is a promising technology for reducing the footprint of optical transceivers, as required by the fast-paced growth of data center traffic. In this work, an SNN nonlinear demapper is designed and evaluated on a simulated intensity-modulation direct-detection link with chromatic dispersion. The SNN demapper is implemented in software and on the analog neuromorphic hardware system BrainScaleS-2 (BSS-2). For comparison, linear equalization (LE), Volterra nonlinear equalization (VNLE), and nonlinear demapping by an artificial neural …
We consider wireless communication systems with compact planar arrays having densely spaced antenna elements in conjunction with one-bit analog-to-digital and digital-to-analog converters (ADCs/DACs). We provide closed-form expressions for the achievable rates with simple linear processing techniques for the uplink as well as the downlink scenarios while taking into account the effects of antenna mutual coupling. In the downlink case, we introduce the concept of non-radiating dithering to combat correlations of the quantization errors. Under higher antenna element density, we show that the per…
Obtaining digital representations of multivariate continuous-time (CT) signals is a challenge encountered in many signal processing systems. In practice, these signals are often acquired to extract some underlying information, i.e., for a specific task. Employing conventional task-agnostic analog-to-digital converters (ADCs), typically designed to minimize the mean squared error (MSE) in reconstructing the CT input signal, can be costly and energy-inefficient in such cases. In this work, we study task-based ADCs, which are designed to obtain a digital representation of a multivariate CT input …
This paper presents a low-power 10-bit 130-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 90 nm CMOS process. The proposed asynchronous ADC consists of a comparator, SAR logic block and two control blocks for the capacitive digital to analog converters (DAC). At a 1.2 V supply and 130 MS/s, the ADC achieves an SNDR of 55.2 dB and consumes 860 uW, resulting in a figure of merit (FOM) of 50.9 fJ/MHz. It achieves an ENOB of 8.8 bits with a differential input range of 1570 mV.
Sensor nodes in a wireless sensor network (WSN) for security surveillance applications should preferably be small, energy-efficient, and inexpensive with in-sensor computational abilities. An appropriate data processing scheme in the sensor node reduces the power dissipation of the transceiver through the compression of information to be communicated. This study attempted a simulation-based analysis of human footstep sound classification in natural surroundings using simple time-domain features. The spiking neural network (SNN), a computationally low-weight classifier derived from an artificia…
dAJC: A 2.02mW 50Mbps Direct Analog to MJPEG Converter for Video Sensor Node using Low-Noise Switched Capacitor MAC-Quantizer with Auto-Calibration and Sparsity-Aware ADC
High-speed high-resolution Analog-to-Digital Conversion is the key part for waveform digitization in physics experiments and many other domains. This paper presents a new fully digital correction of mismatch errors among the channels in Time Interleaved Analog-to-Digital Converter (TIADC) systems. We focus on correction with wide-band input signal, which means that we can correct the mismatch errors for any frequency point in a broad band with only one set of filter coefficients. Studies were also made to show how to apply the correction algorithm beyond the base band, i.e. other Nyquist zones…
Human lives are improving with the widespread use of cutting-edge digital technology like the Internet of Things (IoT). Recently, the pandemic has shown the demand for more digitally advanced IoT-based devices. International Data Corporation (IDC) forecasts that by 2025, there will be approximately 42 billion of these devices in use, capable of producing around 80 ZB (zettabytes) of data. So data acquisition, processing, communication, and visualization are necessary from a functional standpoint. Indicating sensors & data converters are the key components for IoT-based applications. The effici…
In this work, we consider a full-duplex (FD) massive multiple-input multiple-output (MIMO) cellular network with low resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Our first contribution is to propose a unified framework for forward link analysis where matched filter precoders are applied at the FD base stations (BSs) under channel hardening. Second, we derive expressions for the signal-to-quantization-plus-interference-plus-noise ratio (SQINR) for general and special cases. Finally, we quantify effects of quantization error, pilot contamination, and fu…
In this work, we consider a full-duplex (FD) massive multiple-input multiple-output (MIMO) cellular network with low-resolution analog-to-digital converters (ADCs) and digital-to-analog converter (DACs). Our first contribution is to provide a unified framework for reverse link (uplink) analysis where matched filters are applied at the FD base stations (BSs) under channel hardening. Second, we derive the expressions of the signal-to-quantization-plus-interference-plus-noise ratio (SQINR) for general and special cases. Finally, we quantify effects of quantization error, pilot contamination, and …
Due to the fundamental limit to reducing power consumption of running deep learning models on von-Neumann architecture, research on neuromorphic computing systems based on low-power spiking neural networks using analog neurons is in the spotlight. In order to integrate a large number of neurons, neurons need to be designed to occupy a small area, but as technology scales down, analog neurons are difficult to scale, and they suffer from reduced voltage headroom/dynamic range and circuit nonlinearities. In light of this, this paper first models the nonlinear behavior of existing current-mirror-b…
In a growing number of applications, there is a need to digitize a (possibly high) number of correlated signals whose spectral characteristics are challenging for traditional analog-to-digital converters (ADCs). Examples, among others, include multiple-input multiple-output systems where the ADCs must acquire at once several signals at a very wide but sparsely and dynamically occupied bandwidth supporting diverse services. In such scenarios, the resolution requirements can be prohibitively high. As an alternative, the recently proposed modulo-ADC architecture can in principle require dramatica…
University of California, Santa Barbara（加州大学圣巴巴拉分校）；Tsinghua University（清华大学）
Recently, backpropagation through time inspired learning algorithms are widely introduced into SNNs to improve the performance, which brings the possibility to attack the models accurately given Spatio-temporal gradient maps. We propose two approaches to address the challenges of gradient input incompatibility and gradient vanishing. Specifically, we design a gradient to spike converter to convert continuous gradients to ternary ones compatible with spike inputs. Then, we design a gradient trigger to construct ternary gradients that can randomly flip the spike inputs with a controllable turnov…
Invariant neuromorphic representations of tactile stimuli improve robustness of a real-time texture classification system
Johns Hopkins School of Medicine（约翰斯·霍普金斯医学院）；University of Chicago（芝加哥大学）；National Institutes of Health（美国国立卫生研究院）；Vanderbilt University（范德堡大学）；Johns Hopkins University（约翰斯·霍普金斯大学）；The University of North Texas Health Science Center（北得克萨斯健康科学中心大学）；Infinite Biomedical Technologies, LLC.（无限生物医学技术有限责任公司）
Due to the limitations of realizing artificial neural networks on prevalent von Neumann architectures, recent studies have presented neuromorphic systems based on spiking neural networks (SNNs) to reduce power and computational cost. However, conventional analog voltage-domain integrate-and-fire (I&F) neuron circuits, based on either current mirrors or op-amps, pose serious issues such as nonlinearity or high power consumption, thereby degrading either inference accuracy or energy efficiency of the SNN. To achieve excellent energy efficiency and high accuracy simultaneously, this paper present…
Spiking neural networks (SNN) provide a new computational paradigm capable of highly parallelized, real-time processing. Photonic devices are ideal for the design of high-bandwidth, parallel architectures matching the SNN computational paradigm. Co-integration of CMOS and photonic elements allow low-loss photonic devices to be combined with analog electronics for greater flexibility of nonlinear computational elements. As such, we designed and simulated an optoelectronic spiking neuron circuit on a monolithic silicon photonics (SiPh) process that replicates useful spiking behaviors beyond the …
Spiking neural networks (SNNs) are distributed trainable systems whose computing elements, or neurons, are characterized by internal analog dynamics and by digital and sparse synaptic communications. The sparsity of the synaptic spiking inputs and the corresponding event-driven nature of neural processing can be leveraged by energy-efficient hardware implementations, which can offer significant energy reductions as compared to conventional artificial neural networks (ANNs). The design of training algorithms lags behind the hardware implementations. Most existing training algorithms for SNNs ha…
Spiking Neural Networks (SNNs) are distributed trainable systems whose computing elements, or neurons, are characterized by internal analog dynamics and by digital and sparse synaptic communications. The sparsity of the synaptic spiking inputs and the corresponding event-driven nature of neural processing can be leveraged by hardware implementations that have demonstrated significant energy reductions as compared to conventional Artificial Neural Networks (ANNs). Most existing training algorithms for SNNs have been designed either for biological plausibility or through conversion from pre-trai…
