LUXOR：一种用于高效压缩树实现的FPGA逻辑单元结构
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations
摘要：
我们提出了两个层次的修改FPGA逻辑单元架构，以提供各种性能和利用率的好处，只有很小的面积开销。在第一层中，我们用一个6输入“异”门来增强现有的商业逻辑单元数据路径，以提高每个元素的表达能力，同时保持向后兼容性。这种新架构与供应商无关，我们将其称为LUXOR。我们还考虑了对Xilinx和Intel FPGA的供应商特定修改的第二层，我们分别将其称为X-LUXOR+和I-LUXOR+。我们证明，压缩机树合成使用广义并行计数器（GPC）的进一步改善所提出的修改。在65 nm工艺节点上使用Intel自适应逻辑模块和Xilinx芯片进行比较研究，结果表明，LUXOR和LUXOR+的硅面积开销分别小于0.5%和5-6%，而延迟增量分别为1-6%和3-9%。我们证明，LUXOR可以提供一个平均减少13-19%的逻辑利用率从各种领域的微基准测试。BNN基准受益最大，平均减少37-47%的逻辑利用率，这是由于我们提出的LUXOR+逻辑单元上的XnorPopcount操作的高效映射。
英文摘要：
We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the irst tier, we augment existing commercial logic cell datapaths with a 6-input XOR gate in order to improve the expressiveness of each element, while maintaining backward compatibility. This new architecture is vendor-agnostic, and we refer to it as LUXOR. We also consider a secondary tier of vendor-speciic modifications to both Xilinx and Intel FPGAs, which we refer to as X-LUXOR+ and I-LUXOR+ respectively. We demonstrate that compressor tree synthesis using generalized parallel counters (GPCs) is further improved with the proposed modifications. Using both the Intel adaptive logic module and the Xilinx slice at the 65nm technology node for a comparative study, it is shown that the silicon area overhead is less than 0.5% for LUXOR and 5-6% for LUXOR+, while the delay increments are 1-6% and 3-9% respectively. We demonstrate that LUXOR can deliver an average reduction of 13-19% in logic utilization on micro-benchmarks from a variety of domains.BNN benchmarks benefit the most with an average reduction of 37-47% in logic utilization, which is due to the highly-efficient mapping of the XnorPopcount operation on our proposed LUXOR+ logic cells.
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